Digital signal modulation system

In a system for processing a digital input signal a method for producing a coded output signal as a function of a change in a parameter including a logic state of said input signal, comprising the steps of:

• generating a first pulse width coded bit with a predetermined duration and a predetermined reference bit width when said input signal represents no change of said parameter;
• generating a second pulse width coded bit when said input signal represents a first type of change in said parameter,
• said step of generating said second coded bit produces a coded bit with a first predetermined change in bit width comprising a predetermined increase in bit width relative to said reference bit width, when said input signal exhibits a logic state change in one direction;
• and
• generating a third pulse width coded bit when said input signal represents a second type of change in said parameter, wherein said first to third pulse width coded bits are different from one another;
• and
• said step of generating said third coded bit produces a third coded bit with a second predetermined change in bit width comprising a predetermined decrease in bit width relative to said reference bit width, when said input signal exhibits a logic state change in another direction.

In a system for processing a digital input signal, a method for producing a coded output signal as a function of a change in a parameter including a logic state of said input signal, comprising the steps of:

• generating a first pulse width coded bit with a predetermined duration and a predetermined reference bit width when said input signal represents no change of said parameter;
• said step of generating said first coded bit produces a coded bit encompassing a predetermined number of clock periods when said input signal does not exhibit a logic state change;
• generating a second pulse width coded bit when said input signal represents a first type of change in said parameter,
• said step of generating said second coded bit produces a coded bit encompassing a first predetermined change in bit width comprising a predetermined increase in clock periods when said input signal exhibits a logic state change in one direction;
• and
• generating a third pulse width coded bit when said input signal represents a second type of change in said parameter, wherein said first to third pulse width coded bits are different from one another;
• and
• said step of generating said third coded bit produces a coded bit with a second predetermined change in bit width relative to said reference bit width encompassing a predetermined decrease in clock periods when said input signal exhibits a logic state change in another direction.

A decoding method for producing a decoded datastream from a received bitstream comprising first, second and third pulse width coded bits representing changes in a single variable parameter of an input datastream, said decoding method comprising the steps of

• generating a first data component representing no change of said parameter, in response to said first coded bit of predetermined duration equal to a multiple of a basic clock period;
• generating a second data component representing a first type of change in said parameter, in response to said second coded bit;
• and
• generating a third data component representing a second type of change in said parameter, in response to said third coded bit, wherein said first to third pulse width coded bits are different in duration from one another by integral multiples of said basic clock period.

A decoding method for producing a decoded datastream from a received bitstream comprising first, second and third pulse width coded bits representing chances in a single variable parameter of an input datastream said decoding method comprising the steps of

• generating a first data component representing no change of said parameter, in response to said first coded bit of predetermined duration equal to a multiple of a basic clock period;
• generating a second data component representing a first type of chance in said parameter, in response to said second coded bit;
• and
• generating a third data component representing a second type of change in said parameter, in response to said third coded bit, wherein said first to third pulse width coded bits are different in duration from one another;
• wherein
• said first coded bit encompasses N predetermined clock periods;
• said second coded bit encompasses N+1 clock periods;
• and
• said third coded bit encompasses N−1 clock periods.