Method of forming an N channel and P channel FINFET device on the same semiconductor substrate

A method of forming a FINFET CMOS device in a silicon on insulator (SOI), layer, comprising the steps of:

• forming said SOI layer on a semiconductor substrate;
• depositing a silicon oxide layer on said SOI layer;
• performing a first anisotropic reactive ion etch (RIE) procedure to define a first fin type structure in said silicon oxide layer and in said SOI layer, and to define a second fin type structure in said silicon oxide layer and in said SOI layer, with said second fin type structure parallel in direction with said first fin type structure;
• growing a silicon dioxide gate insulator layer on sides of fin type structures;
• depositing a conductive layer;
• performing a second anisotropic RIE procedure to form a conductive gate structure traversing, and normal in direction to, said fin type structures;
• depositing a silicon nitride layer;
• performing a third anisotropic RIE procedure to form a silicon nitride spacer on sides of the portions of said fin type structures not covered by said conductive gate structure, and on sides of said conductive gate structure;
• removing said silicon oxide layer from portions of said fin type structures not covered by said conductive gate structure, exposing a first SOI shape of said first fin type structure, and exposing a second SOI shape of said second fin type structure;
• depositing a first doped insulator layer;
• removing said first doped insulator layer from a region overlying said second fin type structure;
• depositing a second doped insulator layer directly overlying said second fin type structure, while said second doped insulator layer overlays said first doped insulator layer in a region in which said first doped insulator layer directly overlays said first fin type structure;
• performing an anneal procedure to create a first source/drain region, of a first conductivity type, in said first SOI shape of said first fin type structure, and to create a second source/drain region, of a second conductivity type, in said second SOT shape of said second fin type structure;
• removing said first doped insulator layer and said second doped insulator layer;
• and
• selectively depositing tungsten on source/drain regions resulting in said FINFET CMOS device, featuring a first metal oxide semiconductor (MOS), device of a first channel type, comprised with said first source/drain region, and featuring a second MOS device of a second channel type, comprised with said second source/drain region.