Flexible SONET access and transmission system

A SONET network interface for interconnecting at least one high speed unit (HSU) with at least two low speed interface units (LSUs) to enable transmission of signals therebetween, the interface comprising:

• a common bus of predetermined bit width for interfacing the at least one HSU unit with each of the at least two LSU units to enable transmission of signals from each of the at least two LSUs to the at least one HSU, and reception of the signals from the at least one HSU to each of the at least two LSUs:
• a first partition bus of the predetermined bit width for interfacing the at least one HSU to a predetermined number of the at least two LSUs, the first partition bus being partitioned into a first bus for interfacing the at least one HSU to a first subset of the at least two LSUs and a second bus for interfacing the at least one HSU to a second subset of the at least two LSUs;
• and
• a second partition bus of the predetermined bit width for interfacing the at least one HSU to a predetermined number of the at least two LSU units, the second partition bus being partitioned into a third bus for interlacing the at least one HSU unit to the first subset of the at least two LSUs and a fourth bus for interfacing the at least one HSU unit with the second subset of the at least two LSUs;
• and
• an expansion shelf containing at least one expansion LSU and an expansion interface unit (ESI) connected to the at least one HSU of a shelf unit for exchanging data between the shelf unit and the expansion shelf;
• wherein the first, second, third, and fourth buses of respective first and second partition buses have a bit width less tar the predetermined bit width to enable increased flexibility of signal transmissions to and from a SONET network;
• wherein the at least one HSU, at least two LSUs, and common, first and second partition buses, are contained in the shelf unit;
• wherein the shelf unit further comprises a system control processor unit (SCU) for controlling the processes of the units contained in the shelf at least one system timing and control synchronization unit (STU) for controlling the timing and synchronization between the units contained in the shelf unit, and at least one power supply unit for powering the units contained in the shelf unit;
• wherein a local area network exists between the shelf unit and the expansion shelf such that LSUs in the expansion shelf can communicate control, alarm or signaling information directly with common-processing HSUs or LSUs in the shelf unit.

A SONET network interface of for interconnecting at least one high speed unit (HSU) with at least two low speed interface units (LSUs) to enable transmission of signals therebetween, the interface comprising:

• a common bus of predetermined bit width for interfacing the at least one HSU unit with each of the at least two LSU units to enable transmission of signals from each of the at least two LSUs to the at least one HSU, and reception of the signals from the at least one HSU to each of the at least two LSUs;
• a first partition bus of the predetermined bit width for interfacing the at least one HSU to a predetermined number of the at least two LSUs, the first partition bus being partitioned into a first bus for interfacing the at least one HSU to a first subset of the at least two LSUs and a second bus for interfacing the at least one HSU to a second subset of the at least two LSUs;
• and
• a second partition bus of the predetermined bit width for interfacing the at least one HSU to a predetermined number of the at least two LSU units, the second partition bus being partitioned into a third bus for interfacing the at least one HSU unit to the first subset of the at least two LSUs and a fourth bus for interfacing the at least one HSU unit with the second subset of the at least two LSUs;
• and
• an expansion shelf containing at least one expansion LSU and an expansion interface unit (ESI) connected to the at least one HSU of a shelf unit for exchanging data between the shelf unit and the expansion shelf;
• wherein the first, second, third, and fourth buses of respective first and second partition buses have a bit width less than the predetermined bit width to enable increased flexibility of signal transmissions to and from a SONET network;
• wherein the at least one HSU, at least two LSUs, and common, first and second partition buses, are contained in the shelf unit;
• wherein the shelf unit further comprises a system control processor unit (SCU) for controlling the processes of the units contained in the shelf, at least one system timing and control synchronization unit (STU) for controlling the timing and synchronization between the units contained in the shelf unit, and at least one power supply unit for powering the units contained in the shelf unit;
• wherein some of the at least two LSU's which perform a common processing function on the first and third buses at a STS-3 rate process all of the data from all LSUs connected to the second and fourth buses and the at least one expansion LSU in the expansion shelf, and wherein in a receive direction, STS-3 data is sent over the first bus from the at least one HSU to the common processing LSU's, processed by the common processing LSU'S, and sent back over the first bus from the common processing LSU's to the at least one HSU, processed received data is subsequently sent from the at least one HSU over the common bus, second bus, fourth bus, and expansion shelf interface to the at least one LSUs, wherein the transmit data from the at least one LSUs that is sent to the at least one HSU over the common bus, second bus, fourth bus, or expansion interface unit is sent by the at least one HSU over the third bus at STS-3 rate to the at least one common processing LSU, the at least one common processing LSU processing the transmit data and sends it back to the at least one HSU for subsequent transmission.

A method for interconnecting at least one high speed unit (HSU) with at least two low speed interface units (LSUs) in a SONET network interface to enable transmission of signals between the HSU and LSUs, the method comprising:

• interfacing the at least one HSU unit with each of the at least two LSU units by means of a common bus of predetermined bit width to enable transmission of signals from each of the at least two LSUs to the at least one HSU, and reception of the signals from the at least one HSU to each of the at least two LSUs;
• interfacing the at least one HSU to a predetermined number of the at least two LSUs by means of a first partition bus of the predetermined bit width, the first partition bus being partitioned into a first bus for interfacing the at least one HSU to a first subset of the at least two LSUs and a second bus for interfacing the at least one HSU to a second subset of the at least two LSUs;
• interfacing the at least one HSU to a predetermined number of the at least two LSU units using a second partition bus of the predetermined bit width, the second partition bus being partitioned into a third bus for interfacing the at least one HSU unit to the first subset of the at least two LSUs and a fourth bus for interfacing the at least one HSU unit with the second subset of the at least two LSUs;
• containing the at least one HSU, at least two LSUs, and the common, first and second partition buses, in a shelf unit;
• providing the shelf unit with a system control processor unit (SCU) for controlling the processes of the units contained in the shelf, at least one system timing and control synchronization unit (STU) for controlling the timing and synchronization between the units contained in the shelf unit, and at least one power supply unit for powering the units contained in the shelf unit;
• providing an expansion shelf containing at least one expansion LSU and an expansion interface unit (ESI);
• connecting the at least one HSU of the shelf unit for exchanging data between the shelf unit and the expansion shelf, and
• providing the expansion shelf with at least one power supply unit for powering the units contained on the expansion shelf;
• and
• aligning the data transmitted from the expansion shelf to the data transmitted from the shelf unit such that the data transmitted from the expansion shelf has the same frame alignment as the data transmitted from the shelf unit relative to the at least one HSU for eliminating the need for frame alignment buffering on the at least one HSU,
• whereby the first, second, third and fourth busses of respective first and second partition buses have a bit width less than the predetermined bit width to enable increased flexibility of signal transmissions to and from a SONET network.

A method for interconnecting at least one high speed unit (HSU) with at least two low speed interface units (LSUs) in a SONET network interface to enable transmission of signals between the HSU and LSUs, the method comprising:

• interfacing the at least one HSU unit with each of the at least two LSU units by means of a common bus of predetermined bit width to enable transmission of signals from each of the at least two LSUs to the at least one HSU, and reception of the signals from the at least one HSU to each of the at least two LSUs;
• interfacing the at least one HSU to a predetermined number of the at least two LSUs by means of a first partition bus of the predetermined bit width, the first partition bus being partitioned into a first bus for interfacing the at least one HSU to a first subset of the at least two LSUs and a second bus for interfacing the at least one HSU to a second subset of the at least two LSUs;
• interfacing the at least one HSU to a predetermined number of the at least two LSU units using a second partition bus of the predetermined bit width, the second partition bus being partitioned into a third bus for interfacing the at least one HSU unit to the first subset of the at least two LSUs and a fourth bus for interfacing the at least one HSU unit with the second subset of the at least two LSUs;
• containing the at least one HSU, at least two LSUs, and the common, first and second partition buses, in a shelf unit;
• providing the shelf unit with a system control processor unit (SCU) for controlling the processes of the units contained in the shelf, at least one system timing and control synchronization unit (STU) for controlling the timing and synchronization between the units contained in the shelf unit, and at least one power supply unit for powering the units contained in the shelf unit;
• providing an expansion shelf containing at least one expansion LSU and an expansion interface unit (ESI);
• connecting the at leas one HSU of the shelf unit for exchanging data between the shelf unit and the expansion shelf;
• and
• a local area network between the shelf unit and the expansion shelf such that LSUs in the expansion shelf can communicate control, alarm, or signaling information directly with common-processing HSUs or LSUs in the shelf unit,
• whereby the first, second, third, and fourth buses of respective first and second partition buses have a bit width less than the predetermined bit width to enable increased flexibility of signal transmissions to and from a SONET network.

A method for interconnecting at least one high speed unit (HSU) with at least two low speed interface units (LSUs) in a SONET network interface to enable transmission of signals between the HSU and LSUs, the method comprising:

• interfacing the at least one HSU unit with each of the at least two LSU units by means of a common bus of predetermined bit width to enable transmission of signals from each of the at least two LSUs to the at least one HSU, and reception of the signals from the at least one HSU to each of the at least two LSUs;
• interfacing the at least one HSU to a predetermined number of the at least two LSUs by means of a first partition bus of the predetermined bit width, the first partition bus being partitioned into a first bus for interfacing the at least one HSU to a first subset of the at least two LSUs and a second bus for interfacing the at least one HSU to a second subset of the at least two LSUs;
• interfacing the at least one HSU to a predetermined number of the at least two LSU units using a second partition bus of the predetermined bit width, the second partition bus being partitioned into a third bus for interfacing the at least one HSU unit to the first subset of the at least two LSUs and a fourth bus for interfacing the at least one HSU unit with the second subset of the at least two LSUs;
• containing the at least one HSU, at least two LSUs, and the common, first and second partition buses, in a shelf unit;
• providing the shelf unit with a system control processor unit (SCU) for controlling the processes of the units contained in the shelf, at least one system timing and control synchronization unit (STU) for controlling the timing and synchronization between the units contained in the shelf unit, and at least one power supply unit for powering the units contained in the shelf unit;
• providing an expansion shelf containing at least one expansion LSU and an expansion interface unit (ESI);
• connecting the at least one HSU of the shelf unit for exchanging data between the shelf unit and the expansion shelf;
• and
• providing the expansion shelf with at least one power supply unit for powering the units contained on the expansion shelf;
• and
• whereby the first second, third, and fourth busses of respective first and second partition buses have a bit width less than the predetermined bit width to enable increased flexibility of signal transmissions to and from a SONET network;
• wherein some of the at least two LSUs which perform a common processing function on the first and third buses at a STS-3 rate process all of the data from all LSUs connected to the second and fourth buses and the at least one expansion LSU in the expansion shelf, and wherein in a receive direction STS-3 data is sent over the first bus from the at least one HSU to the common processing LSU's, processed by the common processing LSU's, and sent back over the first bus from the common processing LSU's to the at least one HSU, processed received data is subsequently sent from the at least one HSU over the common bus, second bus, fourth bus, and expansion shelf interface to the at least one LSUs, wherein the transmit data from the at least one LSUs that is sent to the at least one HSU over the common bus, second bus, fourth bus, or expansion interface unit is sent by the at least one HSU over the third bus at STS-3 rate to the at least one common processing LSU, the at least one common processing LSU processing the transmit data and sends it back to the at least one HSU for subsequent transmission.