Frequency control apparatus and digital signal reproducing apparatus

A frequency control apparatus for controlling a pull-in process of a phase-locked loop circuit which outputs a signal for accurately obtaining the data from an inputted reproduced signal at predetermined time intervals in a phase-locked manner, said frequency control apparatus comprising:

• n pieces of cross detectors having n pieces of threshold levels different from each other and smaller than a maximum amplitude of said inputted reproduced signal, wherein n is an integer equal to or larger than 3, each cross detector incrementing a count value in response to a change of said inputted reproduced signal across a threshold level of said each cross detector and outputting an accumulated count value as a cross count value, each cross detector outputting a transitional timing signal;
• n pieces of transitional length detectors each detecting a maximum transitional length based on the transitional timing signal produced from a corresponding one of said n pieces of cross detectors;
• reset means for comparing each of the cross count values outputted from said n pieces of cross detectors with a common reference value and producing a reset signal when one of said cross count values agrees with said common reference value to reset all of said n pieces of cross detectors and said transitional length detectors;
• selecting means for selecting a maximum transitional length detected by the transitional length detector which receives the cross count value agreeing with said common reference value from one of said n pieces of cross detectors;
• and
• a comparing circuit for detecting a deviation of said maximum transitional length selected by said selecting means relative to a proper value and for producing an error signal based on a detected deviation, and further for outputting said error signal to a loop filter in said phase-locked loop circuit.

A digital signal reproducing apparatus comprising:

• control means for performing at least one of a DC control for controlling the DC level of an inputted reproduced signal or controlling threshold levels based on a DC error signal and a gain control for controlling the amplitude of said inputted reproduced signal or controlling threshold clearances based on a gain error signal;
• a cross detecting section having three or more threshold levels different from each other and smaller than a maximum amplitude of said reproduced signal obtained from said control means, incrementing a count value for each threshold level in response to a change of said reproduced signal across said each threshold level, clearing all of count values when the count value of any threshold level reaches a preset value, and restarting said increment operation of said count value for each threshold level in response to the change of said reproduced signal across said each threshold level;
• a phase-locked loop circuit for generating a bit clock;
• and
• an error detecting section for generating at least one of said DC error signal and said gain error signal based on a relative relationship between the count values of said threshold levels at the time the count value of any threshold level reaches said preset value,
• wherein said error detecting section generates said DC error signal so as to shift the DC level of said reproduced signal toward a threshold level corresponding to a smallest count value among said count values, and
• said error detecting section is responsive to a first count value corresponding to a central threshold level and, when said first count value reaches said preset value, compares each of second count values other than said first count value with a predetermined value which is smaller than said first count value, and generates said gain error signal to increase the gain in a case where said second count values are smaller than said predetermined value and also to decrease the gain in a case where said second count values are larger than said predetermined value and smaller than said first count value.

A digital signal reproducing apparatus comprising:

• control means for performing at least one of a DC control for controlling the DC level of an inputted reproduced signal or controlling threshold levels based on a DC error signal and a gain control for controlling the amplitude of said reproduced signal or controlling threshold clearances based on a gain error signal;
• a cross detecting section having three or more threshold levels different from each other and smaller than a maximum amplitude of said reproduced signal obtained from said control means, incrementing a count value for each threshold level in response to a change of said reproduced signal across said each threshold level, clearing all of count values when the count value of any threshold level reaches a preset value, and restarting said increment operation of said count value for each threshold level in response to the change of said reproduced signal across said each threshold level;
• an error detecting section for generating at least one of said DC error signal and said gain error signal based on a relative relationship between the count values of said threshold levels at the time the count value of any threshold level reaches said preset value;
• phase comparing means for generating a phase error signal with respect to the reproduced signal outputted from said control means or a calculated signal derived from said reproduced signal;
• a loop filter for receiving said phase error signal;
• and
• an oscillator for receiving an output signal of said loop filter as a control voltage and generating a bit clock,
• wherein said error detecting section generates said DC error signal so as to shift the DC level of said reproduced signal toward a threshold level corresponding to a smallest count value among said count values, and
• said error detecting section is responsive to a first count value corresponding to a central threshold level and, when said first count value reaches said preset value, compares each of second count values other than said first count value with a predetermined value which is smaller than said first count value, and generates said gain error signal to increase the gain in a case where said second count values are smaller than said predetermined value and also to decrease the gain in a case where said second count values are larger than said predetermined value and smaller than said first count value, and further said error detecting section generates a frequency error signal for controlling the characteristics of said loop filter based on a detected deviation of a bit clock count value relative to a proper value at the time the count value of any threshold level reaches said preset value.