Integrated circuit memory array with fast test mode utilizing multiple word line selection and method therefor

In an integrated circuit having a fully-decoded array of passive element memory cells, each memory cell comprising an anti-fuse and associated with one of a plurality of X-lines and one of a plurality of Y-lines, a method of operating the memory array comprising the steps of:

• selecting at least a first Y-line;
• in a first mode of operation, selecting an X-line associated with the first selected Y-line to impress a read bias across a corresponding memory cell coupled between the selected X-line and the first selected Y-line;
• in a second mode of operation, selecting a first plurality of X-lines associated with the first selected Y-line to impress a read bias across each of a corresponding first plurality of selected memory cells respectively coupled between the first plurality of selected X-lines and the first selected Y-line;
• in both the first and second modes of operation:
• enabling a first read circuit having an input coupled to the first selected Y-line;
• generating a first read signal on an output of the first read circuit having a first value if an aggregate read current through the one or more selected memory cells exceeds a respective threshold level;
• and
• generating an output signal derived at least from the first read signal.

An integrated circuit comprising:

• a fully-decoded memory array of memory cells, each memory cell coupled to one of a plurality of X-lines and one of a plurality of Y-lines, wherein each Y-line is associated with a plurality of X-lines by virtue of the memory cells respectively coupled therebetween;
• means for simultaneously selecting a plurality of memory cells arranged in at least one group of memory cells;
• means for determining whether an aggregate read current greater than a particular value flows through the selected memory cells in each respective group;
• means for generating one or more output signals numbering less than the number of simultaneously selected memory cells, each respective output signal for indicating whether a read current greater than the particular value flows through one or more selected memory cells of each group of memory cells respectively associated therewith.

A method for testing a fully-decoded memory array of programmable memory cells, the method comprising the steps of:

• (a) identifying a maximum acceptable value of read current that would result from applying a given voltage across a defined group of unprogrammed memory cells;
• (b) applying the given voltage across a first group of memory cells to be tested;
• (c) sensing a current through the first group of memory cells from step (b);
• and
• (d) comparing the current of step (c) with the value of step (a).

An integrated circuit comprising:

• a fully-decoded memory array of programmable memory cells, each memory cell coupled to an associated X-line and an associated Y-line;
• a first X-line circuit normally configured to select one of a first plurality of X-lines associated with a first selected Y-line but configurable, during a test mode, to select more than one of the X-lines associated with the first selected Y-line;
• and
• a first Y-line sense circuit for sensing, when enabled, a read current on the first selected Y-line;
• wherein, during the test mode, the X-line decoder is configured to select more than one of the first plurality of X-lines when the first Y-line sense circuit is enabled.