Selection circuit for accurate memory read operations
AssigneeAdvanced Micro Devices, Inc.
InventorsBinh Q. Le, Michael Achter, Lee Cleveland, Pauling Chen
Life of this patent
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Abstract
A selection circuit for sensing current in a target cell during a memory read operation is disclosed. According to one embodiment, the selection circuit comprises a sensing circuit selector connected to a sensing circuit and a ground selector connected to ground. The ground selector connects a first bit line of the target cell to ground, and the sensing circuit selector connects a second bit line of the target cell to the sensing circuit. The sensing circuit selector also connects a third bit line of a first neighboring cell to the sensing circuit. The first neighboring cell shares the second bit line with the target cell.
Claims25
A selection circuit for sensing current in a target cell during a memory read operation, said selection circuit comprising:
- a ground selector connected to ground, said ground selector connecting a first bit line of said target cell to ground;
- and
- a sensing circuit selector connected to a sensing circuit, said sensing circuit selector connecting a second bit line of said target cell to said sensing circuit, said sensing circuit selector further connecting a third bit line of a first neighboring cell to said sensing circuit during said read operation, said first neighboring cell adjacent to said target cell, said first neighboring cell sharing said second bit line with said target cell.
A selection circuit for sensing current in a target cell during a memory read operation, said selection circuit comprising:
- first selector means for connecting a bit line to ground, said second selector means comprising a ground selector, said ground selector connecting a first bit line of said target cell to ground;
- and
- second selector means for connecting a bit line to a sensing circuit;
- said first selector means comprising a sensing circuit selector, said sensing circuit selector connecting a second bit line of said target cell to said sensing circuit, said sensing circuit selector further connecting a third bit line of a first neighboring cell to said sensing circuit during said read operation, said first neighboring cell adjacent to said target cell, said first neighboring cell sharing said second bit line with said target cell.
A selection circuit for sensing current in a target cell during a memory read operation, said selection circuit comprising a ground selector connected to ground, said ground selector connecting a first bit line of said target cell to ground, said selection circuit further comprising a sensing circuit selector connected to a sensing circuit, said sensing circuit selector connecting a second bit line of said target cell to said sensing circuit, said selection circuit being characterized by:
- said sensing circuit selector further connecting a third bit line of a first neighboring cell to said sensing circuit during said read operation, said first neighboring cell adjacent to said target cell, said first neighboring cell sharing said second bit line with said target cell.
A selection circuit for sensing current in a target cell during a memory read operation, said selection circuit comprising:
- a ground selector connected to ground, said ground selector connecting a first bit line of said target cell to ground;
- a sensing circuit selector connected to a sensing circuit, said sensing circuit selector connecting a second bit line of said target cell to said sensing circuit;
- and
- a precharge circuit selector connected to a precharge circuit, said precharge circuit selector connecting a third bit line of a first neighboring cell to said precharge circuit during said read operation, said precharge circuit selector further connecting a fourth bit line of a second neighboring cell to said precharge circuit during said read operation, said second neighboring cell adjacent to said first neighboring cell, said second neighboring cell sharing said third bit line with said first neighboring cell.
Dependencies are inferred from the claim text.