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US 6,768,348 B2Granted
Sense amplifier and electronic apparatus using the same
AssigneeSemiconductor Energy Laboratory Co., Ltd.
InventorsYutaka Shionoiri, Kiyoshi Kato, Munehiro Azami
Life of this patent
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Abstract
A sense amplifier according to the present invention for detecting a potential difference of signals input to a first input terminal and a second input terminal, includes a first means for applying voltages corresponding to threshold voltages of first and second transistors to gate-source voltages of the first and second transistors, and a second means for transferring signals input to the first and second input terminals to gates of the first and second transistors. In this case, a threshold variation of the first and second transistors is corrected.
Claims12
A sense amplifier for detecting a potential difference of signals input to a first input terminal and a second input terminal, comprising:
- a first, second, third, fourth, fifth, sixth, seventh, eighth, and ninth switches;
- a first, second, third, and fourth capacitor, wherein a second terminal of the first capacitor is electrically connected to a first terminal of the sixth switch and a first terminal of the seventh switch, and a second terminal of the second capacitor is electrically connected to a first terminal of the eighth switch and a first terminal of the ninth switch;
- a first and a second power source;
- a first PMOS transistor comprising a source electrically connected to the first power source, a drain electrically connected to a first terminal of the first switch, and a gate electrically connected to the drain;
- a second PMOS transistor comprising a source electrically connected to the first power source, a drain electrically connected to a first terminal of the second switch, and a gate electrically connected to the drain of the first PMOS transistor;
- a first NMOS transistor comprising a gate electrically connected to a second terminal of the third switch, a first terminal of the first capacitor, and a first terminal of the second capacitor;
- a first NMOS transistor comprising a gate electrically connected to a second terminal of the third switch, a first terminal of the first capacitor, and a firm terminal of the second capacitor;
- a second NMOS transistor comprising a gate electrically connected to a second terminal of the fourth switch, a first terminal of the third capacitor and a first terminal of the fourth capacitor, wherein both sources of the first and second NMOS transistors are electrically connected to a first terminal of the fifth switch, a second terminal of the second capacitor and a second terminal of the fourth capacitor;
- and
- an output terminal electrically connected to the drain of the second PMOS transistor;
- wherein a second terminal of the first switch is electrically connected to a drain of a first NMOS transistor and a first terminal of the third switch, and a second terminal of the second switch is electrically connected to a drain of the second NMOS transistor and a fist terminal of the fourth switch, and
- wherein a second terminal of the fifth switch is electrically connected to the second power source, a second terminal of the sixth switch is electrically connected to the first input terminal, a second terminal of the seventh switch is electrically connected to the second power source, a second terminal of the eighth switch is electrically connected to the second input terminal, and a second terminal of the ninth switch is electrically connected to the second power source.
9 more elements
A sense amplifier for detecting a potential difference of signals input to a first input terminal and a second input terminal, comprising:
- a first and a second power source;
- a first, second, third, fourth, and fifth switches, wherein a second terminal of the fifth switch is electrically connected to the second power source;
- a first, second, third, and fourth capacitor, wherein a second terminal of the first capacitor is electrically connected to the first input terminal, and a second terminal of the second capacitor is electrically connected to the second input terminal;
- a first PMOS transistor comprising a source electrically connected to the first power source, a drain electrically connected to a first terminal of the first switch, and a gate electrically connected to the drain;
- a second PMOS transistor comprising a source electrically connected to the first power source, a drain electrically connected to a first terminal of the second switch, and a gate electrically connected to the drain of the first PMOS transistor;
- a first NMOS transistor comprising a gate electrically connected to a second terminal of the third switch, a first terminal of the first capacitor, and a first terminal of the second capacitor;
- a second NMOS transistor comprising a gate electrically connected to a second terminal of the fourth switch, a first terminal of the third capacitor and a first terminal of the fourth capacitor, wherein both sources of the first and second NMOS transistors are electrically connected to a first terminal of the fifth switch, a second terminal of the second capacitor and a second terminal of the fourth capacitor;
- and
- an output terminal electrically connected to a drain of the second PMOS transistor.
6 more elements
Dependencies are inferred from the claim text.