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US 6,765,517 B1Granted
Variable order sigma-delta modulator
AssigneeU.S. Philips Corporation
InventorDanish Ali
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AssigneeU.S. Philips Corporation
InventorDanish Ali
Estimating the term…
A Sigma-Delta modulator(10) comprises a signal put(34) coupled to a forward filter comprising a series connection of a plurality of N summing stages(28, 30, 32), where N is an integer of at least 2, alternating with a corresponding plurality of integrating stages(40, 42, 44) and an analogue to digital converter(ADC)(18) having an input coupled to an output of the Nth integrating stage(44) and an output. A feedback filter comprises a feedback coupling from the output of the ADC(18) to a digital to analogue converter(DAC)(26) which is coupled to an input of each of the summing stages by way of respective weights(46, 48, 50). Control means(66) including switching means (58, 64) are provided for changing the order of the modulator. To reduce the order and increase the bandwidth, the control means by-passes the first(40) of the integrating stages and uses the second(42) of the integrating stages as a first of the integrating stages and vice versa to increase the order and decrease the bandwidth.
A Sigma-Delta modulator comprising a signal input, a plurality of N integrating stages, where N is an integer of at least 2, a corresponding plurality of summing stages coupled to an input of a respective one of the integrating stages, an output of the first to the (N−1)th summing stages being coupled to an input of the second to the Nth integrating stage, respectively, an analogue to digital converter(ADC) having an input coupled to an output of the Nth integrating stage and an output, a feedback coupling from the ADC to a digital to analogue converter(DAC) which is coupled to an input of each of the summing stages, means for sampling the ADC and DAC, and control means for changing the order of the modulator, said control means comprising means for disconnecting the first of the integrating stages and using the second of the integrating stages as a first of the integrating stages.
A receiver comprising means for frequency down converting an input signal to an IF signal, bandpass filtering means and a Sigma-Delta modulator comprising a signal input, a plurality of N integrating stages, where N is an integer of at least 2, a corresponding plurality of summing stages coupled to an input of a respective one of the integrating stages, an output of the first to the (N−1)th summing stages being coupled to an input of the second to the Nth integrating stage, respectively, an analogue to digital converter(ADC) having an input coupled to an output of the Nth integrating stage and an output, a feedback coupling from the ADC to a digital to analogue converter(DAC) which is coupled to an input of each of the summing stages, means for sampling the ADC and DAC, and control means for changing the order of the modulator, said control means comprising means for disconnecting the first of the integrating stages and using the second of the integrating stages as a first of the integrating stages.
Dependencies are inferred from the claim text.