Device structure and method for reducing silicide encroachment

A semiconductor device comprising:

• an isolation region formed in a substrate, said isolation region having a top surface extending less than 1500 Å above a substrate surface;
• a silicon gate electrode formed on a gate dielectric formed on said substrate surface, said silicon gate electrode having a first thickness;
• a gate silicide layer formed on said silicon gate electrode, said gate silicide layer having a second thickness, said second thickness greater than said first thickness;
• a pair of sidewall spacers on opposite sides of said gate electrode, said sidewall spacers having a height of at least 200Å above the second thickness of the gate silicide layer, and said sidewall spacers each having a width less than 300Å;
• a pair of source/drain regions formed on opposite sides of said silicon gate electrode;
• and
• a source/drain silicide layer formed on said source/drain regions, said source/drain silicide layer having said second thickness and wherein the top surface of said source/drain silicide layer has a height less than the top surface of said isolation region.