Method of packaging a plurality of devices utilizing a plurality of lead frames coupled together by rails

A method of making a plurality of chip devices, the method comprising:

• providing a plurality of top leadframes coupled to one another with a pair of rails;
• flipping a bumped die including a source and gate solder bump array on each top leadframe such that each bumped die contacts the gate and source pads of topframe;
• and
• providing a plurality of bottom leadframes being coupled to one another with a pair of rails;
• flipping the top leadframes onto the plurality of bottom leadframes such that a bumped die is between each top leadframe and a corresponding bottom leadframe.

A method of making a plurality of chip devices, the method comprising:

• providing a plurality of top leadframes coupled to one another with a pair of rails;
• providing a plurality of bottom leadframes coupled to one another with a pair of rails, each bottom leadframe including a die attach pad;
• placing a bumped die including a source and gate array on each die attach pad of each bottom leadframe;
• and
• coupling the top and bottom leadframe rails together such that each bumped die contacts the solder bumps of a corresponding top leadframe.