Integrated circuits with scalable design
AssigneeAnadigics, Inc.
InventorsHamid Reza Rategh, Mehdi Frederik Soltan
Life of this patent
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Abstract
A method for designing at least one mask for manufacturing an integrated circuit is disclosed. The method may include generating a schematic; entering data representing transistors of the set into a computer-aided design system; identifying transistors expected to be subject to voltage levels beyond the bounds of a power rail and a ground rail; designating robust geometries such transistors and operating the computer-aided design system to generate mask or masks. Integrated circuits of scalable design are also disclosed.
Claims8
A method for designing at least one mask for manufacturing an integrated circuit comprising:
- generating a schematic for the integrated circuit, the integrated circuit comprising a set of transistors;
- entering data representing each transistor of the set into a computer-aided design system;
- identifying a first subset of the set of transistors implementing an analog circuit comprising a cascode wherein the transistors of the first subset are expected to be subject to voltage levels beyond the bounds of a power rail and a ground rail of the integrated circuit during normal operation;
- designating, in the computer-aided design system, robust geometries for the transistors of the first subset;
- and
- operating the computer-aided design system to generate the at least one mask.
An integrated circuit comprising:
- a semiconductor die formed using at least one mask designed by the acts of:
- generating a schematic for the integrated circuit, the integrated circuit comprising a set of transistors;
- entering data representing each transistor of the set into a computer-aided design system;
- identifying a first subset of the set of transistors implementing an analog circuit comprising a cascode wherein the transistors of the first subset are expected to be subject to voltage levels beyond the bounds of a power rail and a ground rail of the integrated circuit during normal operation;
- designating, in the computer-aided design system, robust geometries for the transistors of the first subset, such that the set of data may be used to generate a plurality of masks for lithography of features having mutually different minimum line widths.
A method for designing a plurality of masks for manufacturing an integrated circuit migrated across a plurality of feature size technologies, each mask associated with a respective feature size technology, the method comprising:
- generating a schematic for the integrated circuit, the integrated circuit comprising a set of transistors;
- entering data representing each transistor of the set into a computer-aided design system;
- identifying a first subset of the set of transistors implementing an analog circuit comprising a cascode wherein the transistors of the first subset are expected to be subject to voltage levels beyond the bounds of a power rail and a ground rail of the integrated circuit during normal operation;
- designating, in the computer-aided design system robust geometries for the transistors of the first subset;
- and
- operating the computer aided design system to generate a first mask associated with a first feature size technology and a second mask associated with a second feature size technology, wherein a respective geometry of each transistor of the first subset is the same for both the first mask and the second mask.
Dependencies are inferred from the claim text.