Split embedded DRAM processor

A method of communicating data between an embedded DRAM processor and a host computing system having an electronics board with a plurality of SIMM interfaces, comprising:

• providing a plurality of embedded DRAMs in the form of bit slice units;
• connecting each of said plurality of bit slice units to said electronics board via respective ones of said SIMM interfaces;
• connecting at least two of said plurality of bit slice units together using at least one bus;
• transferring data between at least one of said bit slice units and said host system;
• and
• transferring data between said at least two bit slice units.

A method of accelerating the processing of data on a host computing system having an electronics board with a plurality of SIMM interfaces, and a host processor in data conmmunication with said electronics board, comprising:

• providing a plurality of embedded DRAMs coprocessors in the form of bit slice units, said bit slice units being adapted for processing data in cooperation with said host processor;
• connecting each of said plurality of bit slice units to said electronics board via respective ones of said SIMM interfaces;
• connecting at least two of said plurality of bit slice units together using at least one bus;
• and
• executing a computer program on at least said host processor, said act of executing initiating the acts of:
• transferring data between at least one of said bit slice units and said host system;
• transferring data between said at least two bit slice units;
• and
• processing at least a portion of said data transferred between said at least one bit slice unit and said host system using at least one of said bit slice units;
• wherein the acts of transferring and processing accelerate the processing of data within said host system.

An embedded dynamic random access memory (DRAM) coprocessor system comprising:

• a plurality of individual bit slice units, each bit slice unit comprising:
• a plurality of DRAM cells;
• a processing unit;
• and
• a communications interface adapted for data communication with at least one other bit slice unit.

In a processing system comprising a host processor coupled to an embedded DRAM coprocessor subsystem, whereby said embedded DRAM coprocessor comprises a plurality of individual bit slice units, each bit slice unit comprising an array of DRAM cells, a processing unit, and a communications interface adapted for data communication with at least one other bit slice unit, a method comprising:

• storing a data structure as a distributed object having components in at least two of said arrays of DRAM cells;
• sending a command from said processor to at least one of said bit slice units over a first data bus adapted to support communication between said processor and said embedded DRAM coprocessor subsystem;
• executing in at least two of said bit slice units at least one program to process portions of said distributed data object stored in respective arrays of DRAM cells using the respective processing unit;
• and
• passing at least one bit of information between said at least two bit slice units using said communications interface in support of the act of executing.