Large crossbar switch implemented in FPGA

A method of implementing a switch in an FPGA having interconnect lines and configuration memory cells, the method comprising:

• building a switch array from interconnect lines in the FPGA;
• and
• configuring the switch array by using the configuration memory cells to turn on selected programmable switches to connect lines in the switch;
• wherein turning on selected programmable switches comprises configuring multiplexers in CLBs of the FPGA.

A method of implementing a switch in an FPGA having interconnect lines and configuration memory cells, the method comprising:

• building a switch array from interconnect lines in the FPGA;
• and
• configuring the switch array by using the configuration memory cells to turn on selected programmable switches to connect lines in the switch;
• wherein the building of the switch array from the interconnect lines in the FPGA comprises connecting routing lines of the FPGA to route input signals to CLBs of the FPGA and route output signals from the CLBs of the FPGA to output pins of the FPGA;
• wherein the step of connecting routing lines of the FPGA to route input signals to CLBs of the FPGA comprises connecting horizontal lines in more than one row of CLBs to receive the same set of input signals.

A method of implementing a switch in an FPGA having interconnect lines and configuration memory cells, the method comprising:

• building a switch array from interconnect lines in the FPGA;
• and
• configuring the switch array by using the configuration memory cells to turn on selected programmable switches to connect lines in the switch;
• wherein the step of configuring the switch array further comprises partially reconfiguring the switch array by partially reconfiguring the FPGA.

A method of implementing a switch in an FPGA having interconnect lines and configuration memory cells, the method comprising:

• building a switch array from interconnect lines in the FPGA;
• and
• configuring the switch array by using the configuration memory cells to turn on selected programmable switches to connect lines in the switch;
• wherein the step of building a switch array from interconnect lines in the FPGA comprises loading a template or configuration data for routing input signals from input pins to CLBs and output signals from CLBs to output pins;
• wherein the output signals pass from one CLB LUT to another on their way to output pins;
• wherein the output signals are temporarily stored in flip-flops within CLBs as they are being passed to output pins.

A method of implementing a switch in an FPGA having interconnect lines and configuration memory cells, the method comprising:

• building a switch array from interconnect lines in the FPGA;
• configuring the switch array by using the configuration memory cells to turn on selected programmable switches to connect lines in the switch;
• and
• connecting a single input pin sequentially to a plurality of interconnect lines and sequentially providing signals between another plurality of interconnect lines and an output pin.

An FPGA implemented as a crossbar switch comprising:

• horizontal interconnect lines connected together to form input signal paths of the crossbar switch;
• CLBs having:
• lookup tables (LUTs) configured to pass one of their input signals to their output terminal;
• input multiplexers (IMUXs) configured to receive input signals from the horizontal interconnect lines, route selected ones of the input signals to lookup tables (LUTs) of the CLBs, the IMUXs being programmed to select between routing a signal on a horizontal line and routing a signal on a vertical line;
• and
• vertical interconnect lines each connected to an output terminal of a LUT and providing a vertical input signal to one of the IMUXs.