Method and structure for buried circuits and devices
AssigneeInternational Business Machines Corporation
InventorsJohn E. Campbell, William T. Devine, Kris V. Srikrishnan
Life of this patent
Estimating the term…
Abstract
A method and structure for fabricating an electronic device using an SOI technique that results in formation of a buried oxide layer. The method includes fabricating at least one first component of the electronic device and fabricating at least one second component of the electronic device, wherein the first component and the second component are on opposite sides of the buried oxide layer, thereby causing the buried oxide layer to perform a function within the electronic device. Entire circuits can be designed around this technique.
Claims20
A method of fabricating an electronic device using an SOI technique, said SOI technique resulting in formation of a buried oxide layer, said method comprising:
- fabricating at least one first component of said electronic device in a first single crystal semiconductor layer;
- and
- depositing a conductive material to fabricate at least one second component of said electronic device in a second single crystal semiconductor layer below and separated from said first single crystal semiconductor layer by said buried oxide layer, wherein one of said second components comprises a component embedded in a substrate beneath said buried oxide layer and said buried oxide layer is thinned locally to perform a function integral to said electronic device;
- said fabricating further comprising:
- forming a trench in said substrate;
- forming an insulator on at least one of a sidewall surface and a bottom surface;
- and
- depositing said conductive material within said trench such that said deposited conductive material and a top surface of said substrate are essentially planar.
A method of fabricating a DRAM cell using an SOI technique on a substrate, said SOI technique resulting in formation of at least one buried oxide layer, said method comprising:
- forming a buried capacitor beneath said buried oxide layer;
- forming a gate beneath said buried oxide layer;
- subsequently, forming an FET source region and drain region on top of said buried oxide layer, said gate being adapted to operate a FET channel between said source region and said drain region;
- and
- interconnecting said capacitor to one of said source region or drain region with a via penetrating said buried oxide layer, said via comprised of a conductive material.
A method of fabricating a DRAM cell using an SOI technique, said SOI technique resulting in formation of at least one buried oxide (BOX) layer, whereby a capacitor for said DRAM cell is formed by a process comprising:
- forming a buried electrode in a substrate, wherein said buried electrode serves as a lower capacitor charge plate;
- and
- forming a diffusion link between the diffusion region of a transistor located on a upper side of said BOX and a region to comprise an upper charge plate of said capacitor, whereby said upper charged plate of said capacitor is formed on an upper side of said BOX when impressing a bias voltage on said buried electrode.
A method of fabricating a dynamic two-phase shift register, said method comprising:
- forming a buried oxide layer using an SOI technique;
- forming a plurality of FET transistors to be in a device layer above said buried oxide layer;
- forming a first clock signal conductor on top of said device layer;
- and
- forming a second clock signal conductor below said device layer, said second clock signal conductor at least partially enclosed by said buried oxide layer.
Dependencies are inferred from the claim text.