Apparatus and technique for maintaining order among requests issued over an external bus of an intermediate network node

A method for maintaining order among read and write requests directed to a same address on a split transaction bus from a processor to a split transaction bus controller of an intermediate network node, the method comprising the steps of:

• receiving a request at an ordering circuit of the controller, the request containing a type of the request and an address of the request;
• storing the request into an entry in a command table and marking the request as pending;
• if the type of the request is a write request, searching the command table and asserting a match bit for each pending read request entry whose request address stored in the entry matches the address of the write request;
• if the request is a write request, loading the request in a low priority output queue;
• if the request is a read request, loading the request in a high priority output queue and asserting a corresponding bit in a read-in-progress register unless the low priority queue contains either a read request or another request whose request address is the same as the request in which case the request is loaded into the low priority output queue;
• when the request reaches the head of the output queue, determining if any match bit is asserted in any entry associated with the request and if the request is a write request, determining if any bit in the read-in-progress register is asserted;
• if any match bit is asserted and if the request is write request any bit in the read-in-progress register is asserted, causing the request to wait at the head of the output queue until all match bits are deasserted and if the request is a write request until all bits in the read-in-progress register are deasserted;
• and
• as each pending read request completes, marking the entry for the read request as non-pending, deasserting the match bit associated with the read request for all entries in the table and deasserting the bit associated with the read request in the read-in-progress register.

Apparatus for maintaining order among read and write requests directed to a same address on a split transaction bus from a processor to a split transaction bus controller of an intermediate network node, the apparatus comprising:

• means for receiving a request at an ordering circuit of the controller, the request containing a type of the request and an address of the request;
• means for storing the request into an entry in a command table and marking the request as pending;
• if the type of the request is a write request, means for searching the command table and asserting a match bit for each pending read request entry whose request address stored in the entry matches the address of the write request;
• if the request is a write request, means for loading the request in a low priority output queue;
• if the request is a read request, means for loading the request in a high priority output queue and asserting a corresponding bit in a read-in-progress register unless the low priority queue contains either a read request or another request whose request address is the same as the request in which case the request is loaded into the low priority queue;
• when the request reaches a head of the output queue, means for determining if match bit is asserted in any entry associated with the request and if the request is a write request, determining if any bit in the read-in-progress register is asserted;
• if any match bit is asserted and if the request is a write request if any bit in the read-in-progress register is asserted, means for stalling the request at the head of the output queue until all match bits are deasserted and if the request is a write request all bits in the read-in-progress register are deasserted;
• and
• as each pending read request completes, means for marking the entry for the read request as non-pending, deasserting the match bit associated with the read request for all entries in the table and deasserting the bit associated with the read request in the read-in-progress register.

A computer readable medium containing executable program instructions for maintaining order among read and write requests directed to a same address on a split transaction bus from a processor to a split transaction bus controller of an intermediate network node, the executable program instructions comprising program instructions for:

• means for receiving a request at an ordering circuit of the controller, the request containing a type of the request and an address of the request;
• storing the request into an entry in a command table and marking the request as pending;
• if the type of the request is a write request, searching the command table and asserting a match bit for each pending read request entry whose request address stored in the entry matches the address of the write request;
• if the request is a write request, loading the request in a low priority output queue;
• if the request is a read request, loading the request in a high priority output queue and asserting a corresponding bit in a read-in-progress register unless the low priority queue contains either a read request or another request whose request address is the same as the request in which case the request is loaded into the low priority output queue;
• when the request reaches the head of the output queue, determining if any match bit is asserted in any entry associated with the request and if the request is a write request, determining if any bit in the read-in-progress register is asserted;
• if any match bit is asserted and if the request is write request any bit in the read-in-progress register is asserted, causing the request to wait at the head of the output queue until all match bits are deasserted and if the request is a write request until all bits in the read-in-progress register are deasserted;
• and
• as each pending read request completes, marking the entry for the read request as non-pending, deasserting the match bit associated with the read request for all entries in the table and deasserting the bit associated with the read request in the read-in-progress register.