Customizable and programmable cell array
AssigneeeASIC Corporation
InventorZvi Or-Bach
Life of this patent
Estimating the term…
Abstract
A personalizable and programmable integrated circuit device including at least first and second programmable logic cells and at least one permanent electrical conductive path interconnecting the at least first and second programmable logic cells for personalization of the integrated circuit device, wherein the at least first and second programmable logic cells are programmable by the application of an electrical signal thereto.
Claims46
A section of an integrated circuit device comprising at least first, second and third metal layers and a first via layer to provide connection between said first metal layer and said second metal layer and a second via layer to provide connection between said second metal layer and said third metal layer,
- wherein at least each of said first metal and said second metal layers consists of a repeating pattern, and wherein at least one of said first via, second via and third metal layers comprises a custom pattern designed to customize the integrated circuit device to a specific user's needs, wherein said first metal layer repeating pattern comprises strips extending generally in parallel to a first axis, and wherein said strips are stepped strips.
A section of an integrated circuit device comprising at least first, second and third metal layers and a first via layer to provide connection between said first metal layer and said second metal layer and a second via layer to provide connection between said second metal layer and said third metal layer,
- wherein at least each of said first metal and said third metal layers consists of a repeating pattern, and wherein at least one of said first via, second via and second metal layers comprises a custom pattern designed to customize the integrated circuit device to a specific user's needs, wherein said third metal layer repeating pattern comprises strips extending generally in parallel to a first axis, and wherein said strips are stepped strips.
A section of an integrated circuit device comprising at least first, second and third metal layers and a first via layer to provide connection between said first metal layer and said second metal layer and a second via layer to provide connection between said second metal layer and said third metal layer,
- wherein at least each of said first metal and said second metal layers consists of a repeating pattern, and wherein at least one of said first via, second via and third metal layers comprises a custom pattern designed to customize the integrated circuit device to a specific user's needs, wherein said first metal layer repeating pattern comprises strips extending generally in parallel to a first axis, wherein at least two vias of first via layer are overlying at least one of said strips connecting said strips to second metal layer, and wherein said at least two vias are in propinquity to a beginning and an end of said at least one of said strips.
A section of an integrated circuit device comprising at least first, second and third metal layers and a first via layer to provide connection between said first metal layer and said second metal layer and a second via layer to provide connection between said second metal layer and said third metal layer,
- wherein at least each of said first metal and said third metal layers consists of a repeating pattern, and wherein at least one of said first via, second via and second metal layers comprises a custom pattern designed to customize the integrated circuit device to a specific user's needs, wherein said third metal layer repeating pattern comprises strips extending generally in parallel to a first axis, wherein at least two vias of second via layer are underlying at least one of said strips connecting said strips to second metal layer, and wherein said at least two vias are in propinquity to a beginning and an end of said at least one of said strips.
A semiconductor device comprising:
- a substrate;
- at least first, second and third metal layers are formed over said substrate, said second metal layer comprising a plurality of generally parallel spaced band structures extending parallel to a first axis, each band structure comprising a multiplicity of second metal layer strips extending perpendicular to said first axis;
- at least one via connecting at least one second metal layer strip with said first metal layer underlying said second metal layer;
- and
- at least one custom layer for customizing the device to a user's specific needs.
A semiconductor device comprising:
- a substrate;
- at least first, second and third metal layers formed over said substrate, said first metal layer comprising a plurality of generally parallel spaced band structures extending parallel to a first axis, each band structure comprising a multiplicity of first metal layer strips extending perpendicular to said first axis;
- at least one via connecting at least one third metal layer strip with said second metal layer underlying said third metal layer;
- and
- at least one custom layer for customizing the device to a user's specific needs.
Dependencies are inferred from the claim text.