Method and apparatus for using fire decoder to correct burst errors in a real-time communications system

An error trapping decoder for correcting error bursts in a communication system using shortened cyclic codes, comprising:

• a first error syndrome shift register, having a structure based on a first factor of a given cyclic code of a given cyclic code family, and a second error syndrome shift register, having a structure based on a second factor of the given cyclic code, the shift registers shifting-in an input binary signal having associated parity check bits generated by a shortened binary cyclic block code belonging to the given cyclic code family;
• a first comparator and a second comparator, coupled to the first and second error syndrome shift registers, receiving data bits stored in a predefined number of low-order and high-order stages of the shift registers, respectively;
• a buffer receiving the input binary signal;
• a correction module coupled to said comparators and said buffer;
• said second error syndrome shift register shifting in a shortened number of zero bits after the shift registers have shifted-in the input binary signal;
• said second comparator determining the number of shifts needed to trap the error burst by monitoring how many zero bits are shifted into said first error syndrome shift register before the data bits in the high-order stages of the shift register have a predetermined pattern indicating the error burst;
• said first comparator determining the number of shifts needed to trap the error burst location, after the shortened number of zero bits are shifted-in, by monitoring how many zero bits are shifted into said second error syndrome shift register before the data bits in the low-order stages of the shift register have a predetermined pattern corresponding to the error burst;
• and
• said correction module, using the shift information determined by said first comparator, locating and correcting the error burst in the input binary signal in the buffer.

An apparatus for correcting an error burst in a communication system using shortened cyclic codes, comprising:

• means for loading data into a first error syndrome register and a second error syndrome register;
• means for shifting shortened zero bits into the second error syndrome register;
• means for shifting a first number of zero bits into the first error syndrome register to trap an error burst pattern associated with an error burst in the data;
• means for determining a second number of zero bit shifts into the second error syndrome register to trap the error burst location in the data;
• and
• means for locating and correcting the error burst in the data by using the second number of zero bit shifts and the error burst pattern.

A computer-readable medium having stored thereon sequences of instructions, the sequences of instructions including instructions, when executed by a digital processor, causes the processor to perform:

• loading data coded with a shortened cyclic code into a first error syndrome register and a second error syndrome register;
• shifting shortened zero bits into the second error syndrome register;
• shifting a first number of zero bits into the first error syndrome register to trap an error burst pattern in the data;
• determining a second number of zero bit shifts into the second error syndrome register to trap an error burst location of the error burst pattern in the data;
• and
• locating and correcting the error burst pattern in the data by using the second number of zero bit shifts and the error burst pattern.

A method for correcting error bursts in a communication system using a shortened cyclic code, comprising:

• loading data coded with a shortened cyclic code into a first error syndrome register and a second error syndrome register;
• shifting shortened zero bits into the second error syndrome register;
• shifting a first number of zero bits into the first error syndrome register to trap an error burst pattern in the data;
• determining a second number of zero bit shifts into the second error syndrome register to trap an error burst location of the error burst pattern in the data;
• and
• locating and correcting the error burst pattern in the data by using the second number of zero bit shifts and the error burst pattern.