Streaming output engine facilitating data transfers between application engines and memory

An apparatus comprising:

• a cache memory;
• a sequencer;
• and
• a set of application engines in communication with said sequencer, wherein said set of application engines includes a streaming output engine including:
• a storage engine including a memory opcode output in communication with said cache memory and a memory address output in communication with said cache memory,
• an alignment circuit in communication with said sequencer and at least one application engine in said set of application engines, wherein said alignment circuit is adapted to align data transfers received from at least one application engine in a data word for a cache line, wherein said alignment circuit has an opcode input in communication with said sequencer to receive an align opcode identifying a size for said data transfers received from said at least one application engine,
• a data buffer including a data output in communication with said cache memory, wherein said data buffer is adapted to provide said data word on said data output for storage in said cache memory at a location having a predetermined byte boundary and being accessed by said storage engine, and
• a mode register in communication with said sequencer to receive a cache line burst value and a store-create value, wherein said cache line burst value indicates whether said storage engine is to perform a cache line burst and said store-create value indicates a condition for said storage engine to issue a store-create command on said memory opcode output, wherein said mode register is in communication with said storage engine to provide said cache line burst value and said store-create value.

An apparatus adapted to transfer data into a memory, said apparatus comprising:

• a sequencer;
• and
• a set of application engines in communication with said sequencer, wherein said set of application engines includes a streaming output engine including:
• a storage engine including a memory opcode output adapted to communicate with said memory and a memory address output adapted to communicate with said memory,
• an alignment circuit in communication with said sequencer and at least one application engine in said set of application engines, wherein said alignment circuit is adapted to align data transfers received from at least one application engine in a data word for storage in said memory, and
• a data buffer including a data output adapted to communicate with said memory, wherein said data buffer is adapted to provide said data word on said data output for storage in said memory at a location having a predetermined byte boundary and being accessed by said storage engine.