Multi-board connection system for use in electronic design automation
AssigneeAxis Systems, Inc.
InventorSharon Sheau-Pyng Lin
Life of this patent
Estimating the term…
Abstract
A high fan-out hub array system and method is provided. The system includes at least one hub that contains user logic that receive signals from various chips and boards, and which quickly turnarounds another signal (based on the logic) out to the desired chips and boards. In a CLKGEN implementation, a global clock is generated in the hub and distributed in a high fan-out manner to all the FPGA logic chips in the system. For a bus resolution application, a hub contains bus resolution logic to resolve bus access requests. It resolves the various requests and delivers the result to all the relevant chips and boards. In a STOPWHEN application, when a STOPWHEN condition has been met, the system delivers a pause signal to all the chips and boards via the high fan-out hubs.
Claims25
A multi-board interconnect system in a motherboard for an electronic system, the motherboard containing a motherboard connector and a host computer system, the host computer including a processor, a main memory, a processor bus system coupled to the processor and main memory, and a system bus coupled to the processor bus, comprising:
- a local bus interconnect separated from the motherboard via the motherboard connector and the local bus interconnect, and including a plurality of first hardware elements and a first logic bus coupling the plurality of first hardware elements and the first logic bus coupled to the local bus interconnect;
- a second board directly coupled to the first board via the local bus interconnect and including a plurality of second hardware elements and a second logic bus coupling the plurality of second hardware elements and the second logic bus coupled to the local bus interconnect, wherein at least one of the plurality of first hardware elements in the first board is coupled to at least one of the plurality of second hardware elements in the second board via the local bus;
- and
- a hub coupling the plurality of first hardware elements and plurality of second hardware elements.
A multi-board connection system in a motherboard for an electronic system, the motherboard containing a motherboard connector and a host computer system, the host computer including a processor, a main memory, a processor bus system coupled to the processor and main memory, and a system bus coupled to the processor bus, comprising:
- an inter-board connection separated from the motherboard connector;
- a first board directly coupled to the motherboard via the motherboard connector and including a plurality of first hardware elements and a first logic bus coupling the plurality of first hardware elements;
- a second board directly coupled to the first board via the inter-board connection and including a plurality of second hardware elements and a second logic bus coupling the plurality of second hardware elements, wherein at least one of the plurality of first hardware elements in the first board is coupled to at least one of the plurality of second hardware elements in the second board via the inter-board connection;
- a third board directly coupled to the second board via the inter-board connection and directly coupled to the motherboard via the motherboard connector, and the third board including a plurality of third hardware elements, wherein at least one of the plurality of second hardware elements in the second board is coupled to at least one of the plurality of third hardware elements in the third board via the inter-board connection;
- and
- a hub coupling the plurality of first hardware elements, second hardware elements, and third hardware elements together so that any hardware element can communicate with any other hardware element in two hops.
A multi-board connection system in a motherboard for an electronic system, the motherboard containing a motherboard connection and a host computer system, the host computer including a processor, a main memory, a processor bus system coupled to the processor and main memory, and a system bus coupled to the processor bus, comprising:
- an interboard connection separated from the motherboard connector;
- a first board directly coupled to the motherboard via the motherboard connector and including at least one row of a plurality of first logic devices and a first logic bus coupling the plurality of first logic devices;
- a second board directly coupled to the first board via the inter-board connection and including at least one row of a plurality of second logic device and a second logic bus coupling the plurality of second logic devices, wherein the first board and second board collectively form an array of a plurality of rows and columns of logic device;
- and
- a hub provided for each column coupling the logic devices in that column, where each of the hubs in each column is coupled together.
Dependencies are inferred from the claim text.