System and method for self-testing and repair of memory modules

A memory module, comprising:

• a plurality of memory devices;
• and
• a memory hub, comprising:
• a memory controller coupled to at least one of the memory devices, the memory controller being responsive to memory requests to the memory devices;
• a self-test module coupled to the memory controller, the self-test module being responsive to a request to test at least one of the memory devices, the self-test module further being operable to identify defective memory locations of the memory devices;
• and
• a repair module coupled to the memory controller, the repair module being responsive to memory requests to defective memory locations of the memory devices to redirect the memory requests to non-defective memory locations of the memory devices.

A computer system, comprising:

• a central processing unit (“CPU”);
• a system controller coupled to the CPU, the system controller having an input port and an output port;
• an input device coupled to the CPU through the system controller;
• an output device coupled to the CPU through the system controller;
• a storage device coupled to the CPU through the system controller;
• a plurality of memory modules, each of the memory modules comprising:
• a plurality of memory devices;
• and
• a memory hub, comprising:
• a self-test module coupled to at least one of the memory devices, the self-test module being responsive to a request to test at least one of the memory devices, the self-test module further being operable to identify defective memory locations of the memory devices;
• a repair module coupled to the self-test module and at least one of the memory devices, the repair module being responsive to memory requests to defective memory locations of the memory devices to redirect the memory requests to non-defective memory locations of the memory devices;
• and
• a communications link coupling the output port of the system controller to the input port of the memory hub in each of the memory modules, and coupling the input port of the system controller to the output port of the memory hub in each of the memory modules.

A computer system, comprising:

• a central processing unit (“CPU”);
• a system controller coupled to the CPU, the system controller having an input port and an output port;
• an input device coupled to the CPU through the system controller;
• an output device coupled to the CPU through the system controller;
• a storage device coupled to the CPU through the system controller;
• a plurality of memory modules, each of the memory modules comprising:
• a plurality of memory devices;
• and
• a memory hub, comprising:
• a memory controller coupled to at least one of the memory devices, the memory controller being responsive to memory requests to the memory devices;
• a self-test module coupled to the memory controller, the self-test module being responsive to a request to test at least one of the memory devices, the self-test module further being operable to identify defective memory locations of the memory devices;
• and
• a repair module coupled to the memory controller, the repair module being responsive to memory requests to defective memory locations of the memory devices to redirect the memory requests to non-defective memory locations of the memory devices;
• a communications link coupling the output port of the system controller to the input port of the memory hub in each of the memory modules, and coupling the input port of the system controller to the output port of the memory hub in each of the memory modules.

A method of testing and repairing each of a plurality of memory devices on each of a plurality of memory modules each of which includes a memory hub, the method comprising:

• using the memory hub in at least one of the memory modules to generate a self-test routine;
• using a generated self-test routine to test at least one of the memory devices in the memory module to identify defective memory locations of the at least one memory device;
• receiving a memory request at the memory hub to access at least one of the memory devices;
• determining at the memory hub if the received memory request is directed to a memory location identified as being a defective memory location;
• if the received memory request is directed to a memory location identified as being a defective memory location, redirecting the memory request to a non-defective location of memory on the memory module;
• and
• if the received memory request is directed to a memory location that was not identified as being a defective memory location, accessing the location in the at least one memory device to which the memory request was directed.