DRAM cells with repressed floating gate memory, low tunnel barrier interpoly insulators

A memory cell, comprising:

• a first source/drain region and a second source/drain region separated by a channel region in a substrate;
• a storage capacitor coupled to the second source/drain region;
• a floating gate opposing the channel region and separated therefrom by a gate oxide;
• a vertical control gate opposing the floating gate, wherein the vertical control gate is separated from the floating gate by a low tunnel barrier intergate insulator;
• and
• wherein the memory cell is controllable to access a first charge representing a data value from the storage capacitor in a first mode of operation and a second charge representing a data value from the floating gate in a second mode of operation, wherein the first charge is accessible without affecting the second charge and the second charge is accessible without affecting the first charge.

A memory cell, comprising:

• a first source/drain region and a second source/drain region separated by a channel region in a substrate;
• a storage capacitor coupled to one of the first and the second source/drain regions;
• a polysilicon floating gate opposing the channel region and separated therefrom by a gate oxide;
• a first metal layer formed on the polysilicon floating gate;
• a metal oxide intergate insulator formed on the metal layer;
• a second metal layer formed on the metal oxide intergate insulator;
• an edge defined polysilicon control gate formed on the second metal layer;
• and
• wherein the storage capacitor is adapted to store volatile data and the floating gate is adapted to store non-volatile data.

A memory array, comprising:

• a number of memory cells, wherein each memory cell includes:
• a first source/drain region and a second source/drain region separated by a channel region;
• a storage capacitor coupled to the second source/drain region;
• a floating gate opposing the channel region and separated therefrom by a gate oxide;
• a control gate opposing the floating gate, wherein the control gate is separated from the floating gate by a low tunnel barrier intergate insulator;
• and
• wherein the memory cell is adapted to operate in a first and a second mode of operation;
• a number of bitlines coupled to the first source/drain regions along a first selected direction in the flash memory array;
• and
• a number of control gate lines coupled to the control gates along a second selected direction in the flash memory array.

An array of memory cells, comprising:

• a number of access transistors, wherein each access transistor includes a first source/drain region and a second source/drain region separated by a body region having a channel region in a substrate;
• a number of storage capacitors coupled to the second source/drain regions;
• a number of floating gates opposing the body regions in the number of pillars and separated therefrom by a gate oxide;
• a number of control gates opposing the floating gates;
• a number of buried bitlines disposed below the number of pillars and coupled to the first source/drain regions along a first selected direction in the array of memory cells;
• a number of control gate lines formed integrally with the number of control gates along a second selected direction in the array of memory cells, wherein the number of control gates are separated from the floating gates by a low tunnel barrier intergate insulator;
• and
• wherein each memory cell in the array of memory cells is controllable to access a first charge representing a data value from the storage capacitor in a first mode of operation and a second charge representing a data value from the floating gate in a second mode of operation, wherein the first charge is accessible without affecting the second charge and the second charge is accessible without affecting the first charge.

An array of memory cells, comprising:

• a number of access transistors, wherein each access transistor includes a first source/drain region and a second source/drain region separated by a body region having a channel region in a substrate;
• a number of storage capacitors coupled to the second source/drain regions;
• a number of floating gates opposing the body regions in the number of pillars and separated therefrom by a gate oxide;
• a number of edge defined control gates opposing the floating gates;
• a number of buried bitlines disposed below the number of pillars and coupled to the first source/drain regions along a first selected direction in the array of memory cells;
• a number of control gate lines formed integrally with the number of edge defined control gates along a second selected direction in the array of memory cells, wherein the number of control gates are separated from the floating gates by a low tunnel barrier intergate insulator;
• and
• wherein the number of storage capacitors are adapted to store volatile data and the number of floating gates are adapted to store non-volatile data.

An electronic system, comprising:

• a processor;
• and
• a memory device coupled to the processor, wherein the memory device includes an array of memory cells, comprising:
• a number of access transistors, wherein each access transistor includes a first source/drain region and a second source/drain region separated by a body region having a channel region in a substrate;
• a number of storage capacitors coupled to the second source/drain regions;
• a number of floating gates opposing the body regions in the number of access transistors and separated therefrom by a gate oxide;
• a number of control gates opposing the floating gates;
• a number of buried bitlines disposed below the number of pillars and coupled to the first source/drain regions along a first selected direction in the array of memory cells;
• a number of control gate lines formed integrally with the number of control gates along a second selected direction in the array of memory cells, wherein the number of control gates are separated from the floating gates by a low tunnel barrier intergate insulator;
• and
• wherein each memory cell in the array of memory cells is adapted to operate in a dynamic mode of operation and a repressed memory mode of operation.

A method of forming a memory cell, comprising:

• forming a first source/drain region and a second source/drain region separated by a channel region in a substrate;
• forming a storage capacitor coupled to one of the first and the second source/drain regions;
• forming a floating gate opposing the channel region and separated therefrom by a gate oxide;
• forming a control gate opposing the floating gate;
• forming a low tunnel barrier intergate insulator to separate the control gate from the floating gate such that the memory cell is operable in a dynamic mode of operation and a repressed memory mode of operation.

A method for forming an array of memory cells, comprising:

• forming a number of access transistors, wherein forming each access transistor includes forming a first source/drain region and a second source/drain region separated by a body region having a channel region in a substrate;
• forming a number of storage capacitors coupled to the second source/drain regions;
• forming a number of floating gates opposing the body regions in the number of pillars and separated therefrom by a gate oxide;
• forming a number of control gates opposing the floating gates;
• forming a number of buried bitlines disposed below the number of pillars and coupled to the first source/drain regions along a first selected direction in the array of memory cells;
• and
• forming a number of control gate lines formed integrally with the number of control gates along a second selected direction in the array of memory cells, wherein the number of control gates are separated from the floating gates by a low tunnel barrier intergate insulator such that each memory cell in the array of memory cells is controllable to access a first charge representing a data value from the storage capacitor in a first mode of operation and a second charge representing a data value from the floating gate in a second mode of operation, wherein the first charge is accessible without affecting the second charge and the second charge is accessible without affecting the first charge.

A method for operating a memory cell having repressed memory, comprising:

• writing to a floating gate of the memory cell using channel hot electron injection, wherein the memory cell includes:
• a first source/drain region and a second source/drain region separated by a channel region in a substrate;
• a storage capacitor coupled to one of the first and the second source/drain regions;
• a floating gate opposing the channel region and separated therefrom by a gate oxide;
• a control gate opposing the floating gate;
• and
• wherein the control gate is separated from the floating gate by a low tunnel barrier intergate insulator;
• erasing charge from the floating gate by tunneling electrons off of the floating gate and onto the control gate;
• and
• sensing a first charge representing a data value from the storage capacitor in a first mode of operation and a second charge representing a data value from the floating gate in a second mode of operation.

A method for operating an array of memory cells, comprising:

• writing to one or more floating gates for a number of memory cells in the array of flash memory cells using channel hot electron injection, the array of flash memory cells includes:
• a number of access transistors, wherein each access transistor includes a first source/drain region and a second source/drain region separated by a body region having a channel region in a substrate;
• a number of storage capacitors coupled to the second source/drain regions;
• a number of floating gates opposing the body regions in the number of pillars and separated therefrom by a gate oxide;
• a number of control gates opposing the floating gates;
• a number of buried bitlines disposed below the number of pillars and coupled to the first source/drain regions along a first selected direction in the array of memory cells;
• and
• a number of control gate lines formed integrally with the number of control gates along a second selected direction in the array of flash memory cells, wherein the number of control gates are separated from the floating gates by a low tunnel barrier intergate insulator;
• erasing charge from the one or more floating gates by tunneling electrons off of the one or more floating gates and onto the number of control gates;
• sensing a first charge representing a data value from the storage capacitor in a dynamic mode of operation;
• and
• sensing a second charge representing a data value from the floating gate in a repressed memory mode of operation.