Method of making wiring and logic corrections on a semiconductor device by use of focused ion beams

A process for producing a semiconductor integrated circuit device having a multilayer wiring structure in which a first insulating film is interposed between an upper-level wiring and a lower-level wiring and the surface of said upper-level wiring has thereon a second insulating film, said method comprising the steps of:

• providing a semiconductor substrate having an integrated circuit formed thereon, said substrate having the multilayer wiring structure formed on its surface, said wiring structure being electrically connected to said integrated circuit;
• selectively removing the second insulating film in said multilayer wiring structure, to form a contact hole;
• selectively removing the upper-level wiring, exposed after selective removal of the second insulating film, to form an opening region in said upper-level wiring, said opening region having a larger diameter than that of said contact hole;
• selectively removing said first insulating film, exposed after selective removal of the upper-level wiring, to form an opening portion which exposes a surface of said lower-level wiring;
• and
• forming a connecting wiring so as to extend over from the inside of said contact hole to a selective region on the surface of said second insulating film, said connecting wiring being electrically connected to said lower-level wiring the surface of which is exposed through said contact hole, said opening region and said opening portion, the connecting wiring being spaced from said upper-level wiring at the opening region.

A process for producing a semiconductor integrated circuit device having a multilayer wiring structure in which a first insulating film is interposed between an upper-level wiring and a lower-level wiring and the surface of said upper-level wiring has thereon a second insulating film, said method comprising the steps of:

• providing a semiconductor substrate having an integrated circuit formed thereon, said integrated circuit including a semiconductor element having a PN junction, said substrate further having the multilayer wiring structure formed on its surface, said wiring structure being electrically connected to said integrated circuit;
• selectively removing the second insulating film in said multilayer wiring structure, by machining with a focused ion beam, to form a contact hole which exposes a surface of the upper-level wiring in this region;
• selectively removing the upper-level wiring, the surface of which is exposed through said contact hole, by an isotropic etching process using said second insulating film as an etching mask, to form an opening region in said upper-level wiring, so as to expose a surface of the first insulating film, said opening region having a larger diameter than that of said contact hole, wherein the step of selectively removing said first insulating film is performed subsequent to the step of selectively removing the upper-level wiring by an isotropic etching process to form the opening region;
• selectively removing said first insulating film, the surface of which is exposed through said contact hole and said opening region, by machining with a focused ion beam to form an opening portion which exposes a surface of said lower-level wiring;
• and
• forming a connecting wiring by a selective CVD method so as to extend over from the inside of said contact hole to a selective region on the surface of said second insulating film, said connecting wiring being electrically connected to said lower-level wiring the surface of which is exposed through said contact hole, said opening region and said opening portion, and said connecting wiring being spaced from said upper-level wiring.

A process for producing a semiconductor integrated circuit device having a multilayer wiring structure in which a first insulating film is interposed between an upper-level wiring and a lower-level wiring and the surface of said upper-level wiring has thereon a second insulating film, said method comprising the steps of:

• providing a semiconductor substrate having an integrated circuit formed thereon, said integrated circuit including a semiconductor element having a PN junction, said substrate further having the multilayer wiring structure formed on its surface, said wiring structure being electrically connected to said integrated circuit;
• selectively removing the second insulating film in said multilayer wiring structure, by machining with a focused ion beam, to form a contact hole which exposes a surface of the upper-level wiring in this region;
• selectively removing the upper-level wiring, the surface of which is exposed through said contact hole, by an isotropic etching process using said second insulating film as an etching mask, to form an opening region in said upper-level wiring, so as to expose a surface of the first insulating film, said opening region having a larger diameter than that of said contact hole;
• selectively removing said first insulating film, the surface of which is exposed through said contact hole and said opening region, by machining with a focused ion beam to form an opening portion which exposes a surface of said lower-level wiring, wherein said opening portion has substantially a same diameter as that of the contact hole;
• and
• forming a connecting wiring by a selective CVD method so as to extend over from the inside of said contact hole to a selective region on the surface of said second insulating film, said connecting wiring being electrically connected to said lower-level wiring the surface of which is exposed through said contact hole, said opening region and said opening portion, and said connecting wiring being spaced from said upper-level wiring, wherein the connecting wiring is formed so as to contact edges of the first and second insulating films respectively providing the opening region and the contact hole, and to be spaced from the edges of the upper-level wiring forming said opening region so as to provide an air gap between said connecting wiring and said edges of the upper-level wiring forming said opening region.

A process for producing a semiconductor integrated circuit device having a multilayer wiring structure in which a first insulating film is interposed between an upper-level wiring and a lower-level wiring and the surface of said upper-level wiring has thereon a second insulating film, said method comprising the steps of:

• providing a semiconductor substrate having an integrated circuit formed thereon, said integrated circuit including a semiconductor element having a PN junction, said substrate further having the multilayer wiring structure formed on its surface, said wiring structure being electrically connected to said integrated circuit;
• selectively removing the second insulating film in said multilayer wiring structure, by machining with a focused ion beam, to form a contact hole which exposes a surface of the upper-level wiring in this region;
• selectively removing the upper-level wiring, the surface of which is exposed through said contact hole, by an isotropic etching process using said second insulating film as an etching mask, to form an opening region in said upper-level wiring, so as to expose a surface of the first insulating film, said opening region having a larger diameter than that of said contact hole;
• selectively removing said first insulating film, the surface of which is exposed through said contact hole and said opening region, by machining with a focused ion beam to form an opening portion which exposes a surface of said lower-level wiring;
• and
• forming a connecting wiring by a selective CVD method so as to extend over from the inside of said contact hole to a selective region on the surface of said second insulating film, said connecting wiring being electrically connected to said lower-level wiring the surface of which is exposed through said contact hole, said opening region and said opening portion, and said connecting wiring being spaced from said upper-level wiring, wherein the connecting wiring is formed so as to be spaced from the edges of the upper-level wiring forming said opening region such that an air gap is provided between said connecting wiring and edges of the upper-level wiring forming said opening region.

A process for producing a semiconductor integrated circuit device having a multilayer wiring structure in which a first insulating film is interposed between an upper-level wiring and a lower-level wiring and the surface of said upper-level wiring has thereon a second insulating film, said method comprising the steps of:

• providing a semiconductor substrate having an integrated circuit formed thereon, said integrated circuit including a semiconductor element having a PN junction, said substrate further having the multilayer wiring structure formed on its surface, said wiring structure being electrically connected to said integrated circuit;
• selectively removing the second insulating film in said multilayer wiring structure, by machining with a focused ion beam, to form a contact hole which exposes a surface of the upper-level wiring in this region;
• selectively removing the upper-level wiring, the surface of which is exposed through said contact hole, by an isotropic etching process using said second insulating film as an etching mask, to form an opening region in said upper-level wiring, so as to expose a surface of the first insulating film, said opening region having a larger diameter than that of said contact hole, wherein said isotropic etching process is a wet etching process, using a mixed solution, comprising phosphoric acid, glacial acetic acid and water, as an etchant;
• selectively removing said first insulating film, the surface of which is exposed through said contact hole and said opening region, by machining with a focused ion beam to form an opening portion which exposes a surface of said lower-level wiring;
• and
• forming a connecting wiring by a selective CVD method so as to extend over from the inside of said contact hole to a selective region on the surface of said second insulating film, said connecting wiring being electrically connected to said lower-level wiring the surface of which is exposed through said contact hole, said opening region and said opening portion, and said connecting wiring being spaced from said upper-level wiring.

A process for producing a semiconductor integrated circuit device having a multilayer wiring structure in which a first insulating film is interposed between an upper-level wiring and a lower-level wiring and the surface of said upper-level wiring has thereon a second insulating film, said method comprising the steps of:

• providing a semiconductor substrate having an integrated circuit formed thereon, said substrate having the multilayer wiring structure formed on its surface, said wiring structure being electrically connected to said integrated circuit;
• selectively removing the second insulating film in said multilayer wiring structure, to form a contact hole;
• selectively removing the upper-level wiring, exposed after selective removal of the second insulating film, to form an opening region in said upper-level wiring, said opening region having a larger diameter than that of said contact hole;
• selectively removing said first insulating film, exposed after selective removal of the upper-level wiring, to form an opening portion which exposes a surface of said lower-level wiring;
• and
• forming a connecting wiring so as to extend over from the inside of said contact hole to a selective region on the surface of said second insulating film, said connecting wiring being electrically connected to said lower-level wiring the surface of which is exposed through said contact hole, said opening region and said opening portion, the connecting wiring being spaced from the upper-level wiring at the opening region, wherein the connecting wiring is spaced from the upper-level wiring by an air gap therebetween.