Hardware and software co-simulation including simulating a target processor using binary translation

A method of simulating an electronic system that includes target digital circuitry and one or more target processors, each with an accompanying user program to be executed on its target processor, the simulation on a host computer system including one or more host processors, the method comprising:

• for each target processor, providing the user program in binary form, and executing a processor simulation process including determining an analyzed version of the user program, and simulating execution of the target processor's user program by executing the analyzed version of the user program on a host processor, determining the analyzed version of the user program including:
• decomposing the user program into linear blocks,
• translating each linear block of the user program into host code that simulate the operations of the linear block,
• storing the host code of each linear block in a host code buffer for the linear block,
• adding timing information into the code in the host code buffer on the time it would take for the target processor to execute the user program, the timing information incorporating target processor instruction timing, the adding of timing information including inserting of dynamic hooks into the corresponding host code in the host code buffer that during execution invoke dynamic mechanisms that may effect timing and that cannot be determined ahead of execution,
• such that while the processor simulation process executes the analyzed version of the user program, the processor simulator accumulates simulation time according to a simulation time frame, the accumulated simulation time accounting for the target processor instruction timing as if the user program was executing on the target processor;
• simulating the target digital circuitry on a hardware simulator operating on the host computer system, the simulating of the target digital circuitry including accumulating timing information;
• and
• passing communication between the processor simulation process and the hardware simulator at significant events, including events that require interaction between the user program and the target digital circuitry.

A method of simulating on a host computer system the execution of a user program on a target processor having a TLB, the method comprising:

• decomposing the user program into linear blocks of target code;
• translating each linear block into host code that simulates the operations of the linear block;
• storing the host code of each linear block in a host code buffer for the linear block;
• for each linear block, inserting dynamic hooks into the host code in the host code buffer that during execution invoke dynamic mechanisms that may effect timing and that cannot be determined ahead of execution, the inserting of dynamic hooks including inserting hooks into the user program to invoke a TLB simulation process for any reference that includes a memory reference that might require a TLB lookup, the TLB simulation process including looking up a simulated TLB having simulated TLB entries;
• for each linear block, adding timing information into the code in the host code buffer on the time it would take for the target processor to execute the user program, the timing information incorporating target processor instruction timing and TLB effects;
• executing the code in the host code buffers;
• and
• accumulating simulation time according to a simulation time frame, the accumulated simulation time accounting for the target processor instruction timing and TLB effects as if the user program was executing on the target processor,
• the TLB simulation process including storing, at execution time, for a target instruction that might require a TLB lookup, a pointer to the simulated TLB entry that results from a lookup of the simulated TLB the first time execution of the target instruction is simulated such that searching the simulated TLB can be avoided the next time the target instruction is executed in simulation.

A method of simulating on a host computer system the execution of a user program on a target processor having a TLB, the method comprising:

• decomposing the user program into linear blocks of target code;
• translating each linear block into host code that simulates the operations of the linear block;
• storing the host code of each linear block in a host code buffer for the linear block;
• for each linear block, inserting dynamic hooks into the host code in the host code buffer that during execution invoke dynamic mechanisms that may effect timing and that cannot be determined ahead of execution, the inserting of dynamic hooks including inserting hooks into the user program to invoke a TLB simulation process for any reference that includes a memory reference that might require a TLB lookup, the TLB simulation process including looking up a simulated TLB having simulated TLB entries;
• for each linear block, adding timing information into the code in the host code buffer on the time it would take for the target processor to execute the user program, the timing information incorporating target processor instruction timing and TLB effects;
• executing the code in the host code buffers;
• and
• accumulating simulation time according to a simulation time frame, the accumulated simulation time accounting for the target processor instruction timing and TLB effects as if the user program was executing on the target processor,
• wherein the attributes of a TLB entry are encoded in the corresponding simulated TLB entry such that the testing of whether or not a virtual address and a page size match an entry of the simulated TLB automatically also checks permission without a separate permissions check required.

A method of simulating on a host computer system the execution of a user program on a target processor having a cache, the method comprising:

• decomposing the user program into linear blocks of target code;
• translating each linear block into host code that simulates the operations of the linear block;
• storing the host code of each linear block in a host code buffer for the linear block;
• for each linear block, inserting dynamic hooks into the host code in the host code buffer that during execution invoke dynamic mechanisms that may effect timing and that cannot be determined ahead of execution, the inserting of dynamic hooks including inserting hooks into the user program to invoke a cache simulation process for any reference that includes a memory reference that might require a cache lookup, the cache simulation process including looking up a simulated cache having simulated cache entries;
• for each linear block, adding timing information into the code in the host code buffer on the time it would take for the target processor to execute the user program, the timing information incorporating target processor instruction timing and cache effects;
• executing the code in the host code buffers;
• and
• accumulating simulation time according to a simulation time frame, the accumulated simulation time accounting for the target processor instruction
• timing and cache effects as if the user program was executing on the target processor,
• the cache simulation process including storing, at execution time, for a target instruction that might require a cache lookup, a pointer to the simulated cache entry that results from a lookup of the simulated cache the first time execution of the target instruction is simulated such that searching the simulated cache can be avoided the next time the target instruction is executed in simulation.

A method of simulating on a host computer system the execution of a user program on a target processor, the method comprising:

• decomposing the user program into linear blocks of target code;
• translating each linear block into host code that simulates the operations of the linear block;
• storing the host code of each linear block in a host code buffer for the linear block;
• for each linear block, inserting dynamic hooks into the host code in the host code buffer that during execution invoke dynamic mechanisms that may effect timing and that cannot be determined ahead of execution;
• for each linear block, adding timing information into the code in the host code buffer on the time it would take for the target processor to execute the user program, the timing information incorporating target processor instruction timing and cache effects;
• for each host code buffer, looking up the next host code buffer to execute and executing the code in the next code buffers in sequence;
• and
• accumulating simulation time according to a simulation time frame, the accumulated simulation time accounting for the target processor instruction timing and cache effects as if the user program was executing on the target processor,
• wherein the looking up the next host code buffer at the conclusion of processing the code in a present host code buffer includes searching for the next host code buffer the first time the present host code buffer is processed, and, after the next host code buffer is found or newly created, storing for the present host code buffer a pointer to the next host code buffer such that the search for the next host code buffer can be avoided the next time the present host code buffer is processed and its next host code buffer is looked up.