Methods and systems for predicting IC chip yield
AssigneeKLA-Tencor Technologies Corporation
InventorsAkella V. S. Satya, Li Song, Robert Thomas Long, Kurt H. Weiner
Life of this patent
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AssigneeKLA-Tencor Technologies Corporation
InventorsAkella V. S. Satya, Li Song, Robert Thomas Long, Kurt H. Weiner
Estimating the term…
Disclosed are methods and apparatus for efficiently managing IC chip yield learning. In general terms, as each wafer lot moves through fabrication, yield information is obtained from each set of test structures for a particular process or defect mechanism. The nature of the yield information is such that it may be used directly or indirectly to predict product wafer test yield. In one implementation, the yield information includes a systematic yield (Y0), a defect density (DD), and a defect clustering factor (α) determined based on the inspected test structure's yield. A running average of the yield information for each process or defect mechanism is maintained as each wafer lot is processed. As a particular wafer lot moves through the various processes, a product wafer-sort test yield may be predicted at any stage in the fabrication process based on the running-average yield information maintained for previously fabricated wafer lots.
A method of managing and predicting product yield for a plurality of semiconductor products, comprising:
A computer program product for managing and predicting product yield for a plurality of semiconductor products, the computer program product comprising:
A yield management system for managing and predicting product yield for a plurality of semiconductor products, the system comprising:
Dependencies are inferred from the claim text.