Low noise correlated double sampling modulation system

A modulation system generating and receiving an analog input signal from an input sensor, said modulation system comprising:

• a switched excitation circuit coupled to excite said input sensor for generating an input voltage step;
• an integrator coupled to sample said input voltage step in synchronous with the excitation of said input sensor and to generate an integrator output signal, said integrator comprising:
• an input capacitor having a first terminal coupled to said input sensor and a second terminal;
• an amplifier having a first input terminal coupled to said second terminal of said input capacitor and an output terminal;
• an accumulation capacitor having a first terminal coupled to said first input terminal of said amplifier and a second terminal providing said integrator output signal;
• a first switch coupled between said first input terminal and said output terminal of said amplifier, said first switch being controlled by a data dependent signal;
• a second switch coupled between said second terminal of said accumulation capacitor and said output terminal of said amplifier, said second switch being controlled by an inverse of said data dependent signal;
• and
• a charge packet generator circuit generating a reference charge packet based on a first voltage and coupling the reference charge packet to said first input terminal of said amplifier;
• and
• a comparator having an input terminal coupled to receive a signal corresponding to said integrator output signal and comparing said integrator output signal to a reference level to generate an output signal at an output terminal, said data dependent signal having a value corresponding to said output signal of said comparator,
• wherein said output signal forms a digital data stream over a plurality of sampling cycles, said digital data stream having an ones density proportional to a magnitude of said input voltage step.

A modulator receiving an input voltage step from an input sensor, said modulator comprising:

• an integrator coupled to sample said input voltage step in synchronous with the excitation of said input sensor and to generate an integrator output signal, said integrator comprising:
• an input capacitor having a first terminal coupled to said input sensor and a second terminal;
• an amplifier having a first input terminal coupled to said second terminal of said input capacitor and an output terminal;
• an accumulation capacitor having a first terminal coupled to said first input terminal of said amplifier and a second terminal providing said integrator output signal;
• a first switch coupled between said first input terminal and said output terminal of said amplifier, said first switch being controlled by a data dependent signal;
• a second switch coupled between said second terminal of said accumulation capacitor and said output terminal of said amplifier, said second switch being controlled by an inverse of said data dependent signal;
• and
• a charge packet generator circuit generating a reference charge packet based on a first voltage and coupling the reference charge packet to said first input terminal of said amplifier;
• and
• a comparator having an input terminal coupled to receive a signal corresponding to said integrator output signal, said comparator comparing said integrator output signal to a reference level to generate an output signal at an output terminal, said data dependent signal having a value corresponding to said output signal of said comparator,
• wherein said output signal forms a digital data stream over a plurality of sampling cycles, said digital data stream having an ones density proportional to a magnitude of said input voltage step.

A method for sampling and digitizing an analog input data source from an input sensor, comprising:

• applying a switched excitation source to said input sensor;
• generating an input voltage step at said input sensor as a result of said application of said switched excitation source;
• AC coupling said input voltage step to an integrator;
• integrating charges corresponding to a transition of said input voltage step on an accumulation capacitor;
• applying to said integrator a reference charge packet based on a first voltage;
• generating a data dependent signal for deactivating or activating said integrator;
• integrating said reference charge packet corresponding to a transition of said first voltage when said data dependent signal has a first value or disregarding said reference charge packet when said data dependent signal has a second value, said transition of said first voltage being opposite to said transition of said input voltage step;
• comparing a signal corresponding to said charges accumulated on said accumulation capacitor with a reference voltage level;
• and
• generating an output signal as a result of said comparing, said data dependent signal having said first value and said second value corresponding to respective logical levels of said output signal;
• wherein after a plurality of sampling cycles, said output signal forms a digital data stream having an ones density proportional to a magnitude of said input voltage step.