Application of single flux quantum pulse interaction to the simultaneous sampling in-phase and quadrature analog-to-digital converter

A superconducting oscillator/counter analog-to-digital converter for providing simultaneous in-phase and quadrature-phase sampling of an RF signal, said converter comprising:

• a superconducting voltage controlled oscillator responsive to the RF signal, said variable controlled oscillator outputting SFQ input pulses at a rate determined by the voltage of the RF signal;
• a superconducting master clock circuit, said master clock circuit generating SFQ clock pulses;
• a superconducting pulse separation circuit responsive to the SFQ input pulses and the SFQ clock pulses, said pulse separation circuit outputting the SFQ clock pulses and the SFQ input pulses in a manner where so that no input pulse is outputted at the same time as an SFQ clock pulse;
• a superconducting pulse splitter circuit responsive to the SFQ input pulses from the pulse separation circuit, said splitter circuit directing the SFQ input pulses into an in-phase line and a quadrature-phase line;
• a superconducting gate control logic circuit responsive to the SFQ clock pulses from the pulse separation circuit, said gate control logic circuit generating in-phase SFQ clock pulses and a quadrature-phase SFQ clock pulses that are 90 degrees apart in phase;
• a superconducting in-phase aperture gate coupled to the in-phase line and being responsive to the in-phase SFQ input pulses, said in-phase aperture gate also being responsive to the in-phase clock pulses, said in-phase aperture gate outputting the in-phase SFQ input pulses on a positive output line or a negative output line in response to the in-phase SFQ clock pulses;
• a superconducting quadrature-phase aperture gate coupled to the quadrature-phase line and being responsive to the quadrature-phase SFQ input pulses, said quadrature-phase aperture gate also being responsive to the quadrature-phase clock pulses, said quadrature-phase aperture gate outputting the quadrature-phase SFQ input pulses on a positive output line or a negative output line in response to the quadrature-phase SFQ clock pulses;
• a superconducting in-phase accumulator responsive to the positive in-phase SFQ input pulses and the negative in-phase SFQ input pulses from the in-phase aperture gate, said in-phase accumulator adding the positive SFQ input pulses and subtracting the negative SFQ input pulses, said in-phase accumulator being responsive to an in-phase integration clock signal from the gate control logic circuit and outputting an in-phase digital sample signal in response to the in-phase integration clock signal;
• and
• a superconducting quadrature-phase accumulator responsive to the positive quadrature-phase SFQ input pulses and the negative quadrature-phase SFQ input pulses from the quadrature-phase aperture gate, said quadrature-phase accumulator adding the positive SFQ input pulses and subtracting the negative SFQ input pulses, said quadrature-phase accumulator being responsive to a quadrature-phase integration clock signal from the gate control logic circuit and outputting a quadrature-phase digital sample signal in response to the quadrature-phase integration clock signal.