Isolated high voltage PMOS transistor

An isolated high-voltage p-type DMOS transistor comprising:

• a layer of p-type semiconductor material;
• an n-well disposed in said layer of p-type semiconductor material, said n-well disposed at an axis of symmetry;
• a first annular p-type region disposed in said n-well about said axis of symmetry, said first annular region forming the source of said transistor;
• an annular shallow trench isolation region disposed in said layer of p-type semiconductor material about said axis of symmetry and spaced apart from an outer perimeter of said first annular p-type region, a distance between an inner perimeter of said shallow trench isolation region and an outer perimeter of said first annular p-type region defining a channel length of the transistor;
• an annular p-well region disposed in said layer of p-type semiconductor material about said axis of symmetry and spaced apart from said inner perimeter of said shallow trench isolation region, an inner perimeter of said annular p-well region disposed outside of said inner perimeter of said annular shallow trench isolation region at a distance such that lateral diffusion of impurity atoms in said p-well begins to increase a surface impurity concentration in said layer of p-type semiconductor material at said inner periphery of said shallow trench isolation region;
• a second annular p-type region disposed in said p-well about said axis of symmetry and outside of said outer perimeter of said shallow trench isolation region, said second annular p-type region forming drain of said transistor;
• and
• an annular gate disposed above and insulated from said layer of p-type semiconductor material, said gate having an inner perimeter aligned with said outer perimeter of said first annular p-type region and an outer perimeter disposed over said shallow trench isolation region.