US 6,748,577 B2 · System for simplifying the programmable memory to logic interface in FPGA

Abstract

A system for simplifying the programmable memory-to-logic interface in field programmable gate arrays (FPGAs) is provided. An interface may be used to isolate the general purpose routing architecture for intra-programmable logic blocks (PLBs) from the random access memory (RAM) address lines, data lines, and control lines. The PLBs and the input-output resources of the FPGA access the embedded memory (or RAM) using dedicated direct interconnects. Certain of these direct interconnects may originate from PLBs in the vicinity of the RAM. The remainder run between the input-output (IO) pads/routing and the RAM blocks. A bus routing architecture is also provided to combine the memories to emulate larger RAM blocks. This bus routing provides interconnection among RAM blocks and is isolated from the PLB routing resources.

Claims38

Dependent claims

A programmable a gate array (PGA) comprising:

at least one embedded memory having a plurality of address lines, data lines, and control lines connected thereto;
a plurality of programmable logic blocks (PLBs);
a plurality of input/outputs (I/Os);
a plurality of routing lines interconnecting said at least one embedded memory, said PLBs, and said I/Os;
an interface for isolating the routing lines from said address lines, data lines, and control lines;
and
a plurality of dedicated connections for connecting said PLBs and said I/Os to said at least one embedded memory.

4 more elements

Dependencies are inferred from the claim text.

System for simplifying the programmable memory to logic interface in FPGA

Life of this patent

System for simplifying the programmable memory to logic interface in FPGA

Life of this patent

Abstract

Claims38