Method and apparatus for testing path delays in a high-speed boundary scan implementation
AssigneeInternational Business Machines Corporation
InventorsJohnny James LeBlanc, Timothy Skergan
Life of this patent
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Abstract
A method and apparatus for testing path delays in a high-speed boundary scan implementation overcomes limitations imposed by pipelined high-speed clocking architectures used in integrated circuits. A special phase hold circuit provides a mechanism for clocking circuits undergoing dynamic tests, permitting the dynamic test to produce proper results when the integrated circuit under test is clocked with a high-speed distributed clock. The functional logic clock enable is pipelined to synchronize the functional mode clock with the test mode clock when the tester mode is switched.
Claims17
A method for performing a path delay test in functional logic within an integrated circuit, said method comprising:
- detecting a start of a tester clock cycle;
- generating an internal clock for clocking said functional logic by dividing a master clock, wherein said internal clock is started in response to a detection of an edge of said tester clock cycle, wherein said internal clock clocks said functional logic to complete said path delay test during said tester clock cycle;
- and
- extending a stop control signal so that said stop control signal extends for a period of said internal clock, wherein said stop control signal is a signal that ends said path delay test.
A test circuit for performing a path delay test in functional logic within an integrated circuit, wherein said test circuit comprising:
- a test clock input for receiving a tester clock;
- a clock generator coupled to said test clock input for generating an internal clock to clock said functional logic, wherein said internal clock is started after a detection of a start of a tester clock cycle, wherein said internal clock clocks said functional logic to complete said path delay test before the end of said tester clock cycle;
- a stop latch for latching a stop signal to indicate an end of said path delay test;
- and
- a stop delay circuit for extending said stop signal until a period of said internal clock has expired.
Dependencies are inferred from the claim text.