Performance monitor system and method suitable for use in an integrated circuit

An integrated circuit (IC) comprising:

• a memory;
• a cache coupled to the memory, the cache to provide a first signal indicative of performance of the cache;
• a core processor coupled to the cache, the core processor to execute contents of one of the memory and the cache, the core processor comprising user-setle attributes, the core processor to provide a second signal in response to a match of the user-settable attributes and the executed contents of the one of the memory and the cache;
• a watchpoint block coupled to the cache and the core processor, the watchpoint block comprising at least one counter, the watchpoint block, in response to the second signal, to monitor the first signal by operating the at least one counter;
• and
• a memory management unit coupled to the watchpoint block, the memory management unit to provide a third signal, the third signal defining performance of the memory management unit.

A method of monitoring performance of a cache associated with a core processor, the method comprising:

• providing a first signal indicative of performance of the cache;
• providing a second signal in response to a match of user-settable attributes of the core processor and information executed by the core processor;
• and
• monitoring, responsive to the second signal, the first signal;
• counting one of a cache hit and a cache miss:
• and storing the one of the cache hit and the cache miss in a memory.