Changing the thread capacity of a multithreaded computer processor

A method to change the thread capacity of a hardware multithreaded computer processing system capable of executing a plurality of threads, said method comprising the steps of:

• (a) performing a test capable of isolating the failure of a register/array uniquely associated with each of said plurality of threads;
• (b) detecting the failure of at least one register/array and recording the thread with which the at least one failed register/array is uniquely associated;
• (c) disabling access to all register/arrays having storage elements accessible by the thread with which the at least one failed register/array is associated by disabling any of a plurality of thread switch control events in a hardware thread switch control register for the thread;
• and
• (d) maintaining access to all storage elements in other register/arrays storing data of other of said plurality of threads not have a detected failure.

A method to change the thread capacity of a hardware multithreaded computer processing system capable of executing a plurality of threads, said method comprising the steps of:

• (a) performing a functional test to isolate the failure of a storage element in a multithreaded register/array, the multithreaded register/array arranged in a matrix of storage cells, each storage cell further comprised of a plurality of storage elements, one of each of said storage elements in each storage cell being accessible by only one of each of the plurality of threads;
• (b) detecting the failure of at least one storage element and recording the particular thread uniquely associated with the at least one failed storage element;
• (c) disabling all storage elements accessible by only the particular thread uniquely associated with the at least one failed storage element;
• and
• (d) routing data for the particular thread to storage elements accessible by other of said plurality of threads.

A method to change the thread capacity of a hardware multithreaded computer processing system capable of executing a plurality of threads, said method comprising the steps of:

• (a) performing a functional test to isolate the failure of a storage element in a multithreaded register/array, the multithreaded register/array arranged in a matrix of storage cells, each storage cell further comprised of a plurality of storage elements each uniquely corresponding to each of the plurality of threads;
• (b) detecting the failure of at least one storage element and recording the particular thread with which the at least one failed storage element is uniquely associated;
• (c) disabling all storage elements uniquely corresponding to the particular thread associated with the at least one failed storage element by generating a thread switch signal by executing microcode instructions in the multithreaded computer to select others of individual storage elements associated with other of said plurality of threads;
• and
• (d) routing data for the particular thread to storage elements uniquely associated with other of said plurality of threads.

A method to change the thread capacity of a hardware multithreaded computer processing system capable of executing a plurality of threads, said method comprising the steps of:

• (a) performing a functional test to isolate the failure of a storage element in a multithreaded register/array, the multithreaded register/array arranged in a matrix of storage cells, each storage cell further comprised of a plurality of storage elements each uniquely corresponding to each of the plurality of threads;
• (b) detecting the failure of at least one storage element and recording the particular thread with which the at least one failed storage element is uniquely associated;
• (c) disabling all storage elements uniquely corresponding to the particular thread associated with the at least one failed storage element by blowing a fuse positioned at all read/write ports connected to all storage elements associated with said fuse;
• and
• (d) routing data for the particular thread to storage elements uniquely associated with other of said plurality of threads.

A multithreaded computer system capable of disabling at least one thread of operation, comprising:

• (a) at least one multithreaded computer processor;
• (b) at least one thread switch control register for each of a plurality of threads of operation in said multithreaded computer processor;
• (c) at least one hardware multithreaded memory/register array having multithreaded storage cells in which each of said storage cells has a storage element uniquely associated with one thread of operation;
• (d) a main memory connected to the at least one multithreaded computer processor;
• (e) a bus interface connecting the multithreaded computer processor and the main memory to at least one of the group consisting of:
• a plurality of data storage devices, one or more external communication networks, one or more input/output devices for providing user input to/from the computer processor;
• (f) a functional test generator to perform a functional test of at least one thread of operation in the at least one multithreaded computer processor during initial bring-up of the processor;
• (g) a storage element failure detector which detects the failure of a storage element uniquely associated with the at least one thread of operation undergoing the functional test;
• and
• (h) a storage element disabler to disable all the storage elements associated with the at least one thread of operation undergoing the functional test in the multithreaded storage cells.