US 6,748,549 B1 · Clocking an I/O buffer, having a selectable phase difference from the system clock, to and from a remote I/O buffer clocked in phase with the system clock

Abstract

Input/output (I/O) clock phase adjustment circuitry for use with I/O buffer circuitry of an integrated circuit chip. In one embodiment, an integrated circuit chip includes a phase adjustment circuit coupled to receive a system clock. The phase adjustment circuit generates an I/O clock coupled to be received by an I/O buffer circuit of an integrated circuit chip for I/O data transfers in a system. The phase adjustment circuit includes a phase locked loop (PLL) circuit coupled to receive the system clock through a first delay circuit. The I/O clock generated by the PLL circuit is received through a second delay circuit at a feedback clock input of the PLL circuit. The first and second delay circuits are used to control the phase of the I/O clock generated by the PLL circuit relative to the system clock. In one embodiment, a third delay circuit is included in an I/O data path of the I/O buffer circuit of the integrated circuit. The third delay circuit enables input and output data transmissions from the integrated circuit to be clocked, in effect, out of phase with the I/O clock generated by phase adjustment circuit.

Claims29

Dependent claims

An apparatus, comprising:

a phase adjustment circuit coupled to receive a system clock and phase control information, the phase adjustment circuit to generate a first input/output (I/O) clock having a selectable phase difference from the system clock, the phase adjustment circuit including a first delay circuit coupled to receive the system clock and coupled to delay the system clock in response to the phase control information;
and
an I/O buffer circuit clocked in response to the first I/O clock to latch I/O data of the apparatus, the I/O buffer circuit coupled to latch the I/O data to and from a remote I/O buffer circuit of a remote apparatus, the remote I/O buffer circuit clocked in response to a remote I/O clock substantially in phase with the system clock.

A system, comprising:

a clock driver circuit coupled to generate a system clock;
a first chip including a first input/output (I/O) buffer circuit and a first phase locked loop circuit coupled receive the system clock and coupled to generate a first I/O clock coupled to clock the first I/O buffer circuit, the first I/O clock substantially in phase with the system clock;
and
a second chip including a second I/O buffer circuit coupled to the first I/O buffer circuit to transfer I/O data between the first and second chips, the second chip including a phase adjustment circuit coupled receive the system clock and coupled to generate a second I/O clock coupled to clock the second I/O buffer circuit, the second I/O clock having a selectable phase difference from the system clock.

1 more element

Dependencies are inferred from the claim text.

Clocking an I/O buffer, having a selectable phase difference from the system clock, to and from a remote I/O buffer clocked in phase with the system clock

Life of this patent

Clocking an I/O buffer, having a selectable phase difference from the system clock, to and from a remote I/O buffer clocked in phase with the system clock

Life of this patent

Abstract

Claims29