Computer peripheral device that remains operable when central processor operations are suspended
AssigneeIntel Corporation
InventorsDavid Bormann, Leslie E. Cline, Frank Hart, Siripong Sritanyarantana
Life of this patent
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Abstract
A peripheral device having a circuit to detect the power management state of a central processor, a first interface to receive data, and a second interface to couple the peripheral device to the central processor. The peripheral device prevents data transfers that would cause the central processor to change from a second power management state to a first power management state if the central processor is in the second power management state.
Claims43
A peripheral device, comprising:
- a first interface to receive data;
- a second interface to couple the peripheral device to a central processor;
- and
- a circuit to detect the power management state of the central processor and prevent the peripheral device from initiating data transfers that would cause the central processor to change from a second power management state to a first power management state if the central processor is in the second power management state.
A computer system comprising:
- a central processor;
- and
- a first peripheral device having
- a first interface to receive data,
- a second interface to couple the first peripheral device to the central processor, and
- a circuit to detect the power management state of the central processor and prevent the first peripheral device from initiating data transfers that would cause the central processor to change from the second power management state to the first power management state if the central processor is in the second power management state.
A system, comprising:
- a sub-system to detect the power management state of a central processor;
- a sub-system to determine whether the central processor is in a first power management state or a second power management state;
- a sub-system to receive data;
- and
- a sub-system to prevent data transfers that would cause the central processor to change from the second power management state to the first power management state if the central processor is in the second power management state.
A method comprising:
- detecting the power management state of a central processor;
- determining whether the central processor is in a first power management state or a second power management state;
- receiving data;
- and
- preventing data transfers that would cause the central processor to change from the second power management state to the first power management state if the central processor is in the second power management state.
A machine-readable medium that provides instructions, which when executed by a processor, causes the processor to perform operations comprising:
- detecting the power management state of a central processor;
- determining whether the central processor is in a first power management state or a second power management state;
- receiving data;
- and
- preventing data transfers that would cause the central processor to change from the second power management state to the first power management state if the central processor is in the second power management state.
A first peripheral device, comprising:
- a first interface to receive data;
- a second interface to couple the first peripheral device to a central processor;
- and
- a peripheral processor coupled to a program store containing machine-readable instructions which, when executed by the peripheral processor, causes the processor to
- detect the power management state of a central processor,
- determine whether the central processor is in a first power management state or a second power management state, and
- preventing data transfers that would cause the central processor to change from the second power management state to the first power management state if the central processor is in the second power management state.
Dependencies are inferred from the claim text.