Hardware loops
AssigneesIntel Corporation, Analog Devices, Inc.
InventorsRavi P. Singh, Charles P. Roth, Gregory A. Overkamp
Life of this patent
Estimating the term…
Abstract
In one embodiment, a programmable processor is configured to support a loop setup instruction. The loop setup instruction may be decoded and a zero offset loop may be detected from the loop setup instruction. The next instruction in the instruction stream may then be immediately issued as a first instruction in a loop. The loop setup instruction may also be used to detect a single instruction loop.
Claims43
A method comprising:
- decoding a loop-setup instruction;
- detecting a zero offset loop from the loop setup instruction by comparing a start offset value in the loop setup instruction to a width of the loop setup instruction, the zero offset loop having zero instructions between the loop setup instruction and a first instruction in the loop;
- and
- issuing a next instruction following the loop-setup instruction as a first instruction in a the zero offset loop.
A method comprising:
- decoding a loop-setup instruction;
- detecting a zero offset loop from the loop setup instruction;
- and
- issuing a next instruction following the loop-setup instruction as a first instruction in a loop, wherein the zero offset loop is detected before loop conditions of the loop are written to a set of registers.
An apparatus comprising:
- a control unit adapted to detect a zero offset loop from a loop setup instruction by comparing a start offset value in the loop setup instruction to a width of the loop setup instruction, the zero offset loop having zero instructions between the loop setup instruction and a first instruction in the loop;
- and
- loop hardware to store an instruction from the zero offset loop.
A system comprising:
- a SRAM memory device;
- and
- a processor coupled to the memory device, wherein the processor includes a control unit adapted to:
- decode a loop-setup instruction;
- detect a zero offset loop from the loop setup instruction by comparing a start offset value in the loop setup instruction to a width of the loop setup instruction, the zero offset loop having zero instructions between the loop setup instruction and a first instruction in the loop;
- and
- issue a next instruction following the loop-setup instruction as a first instruction in a loop.
A system comprising:
- a SRAM memory device;
- and
- a processor coupled to the memory device, wherein the processor includes a control unit adapted to:
- decode a loop-setup instruction;
- detect a zero offset loop from the loop setup instruction;
- and
- issue a next instruction following the loop-setup instruction as a first instruction in a loop, wherein the control unit is adapted to detect the zero offset loop before loop conditions of the loop get written to a set of registers.
The system as in claimed 20, wherein the control unit is adapted to issue the next instruction from the loop register during a subsequent iteration of the loop.
A method comprising:
- decoding a loop-setup instruction;
- detecting from the loop setup instruction that the top and bottom of a loop are pointing to the same instruction;
- and
- immediately after detecting the top and bottom of a loop are pointing to the same instruction, performing a single instruction loop in a decode stage of a pipeline.
An apparatus comprising:
- a control unit adapted to detect from a loop setup instruction that the top and bottom of a loop are pointing to the same instruction and immediately after detecting the top and bottom of a loop are pointing to the same instruction, performing a single instruction loop starting in a decode stage of a pipeline;
- and
- loop hardware to store the single instruction.
A system comprising:
- an SRAM memory device;
- and
- a processor coupled to the memory device, wherein the processor includes a control unit adapted to:
- decode a loop-setup instruction;
- detect from the loop setup instruction that the top and bottom of a loop are pointing to the same instruction;
- and
- immediately after detecting the top and bottom of a loop are pointing to the same instruction, perform a single instruction loop starting in a decode stage of a pipeline.
Dependencies are inferred from the claim text.