Method and apparatus for utilizing renamed registers based upon a functional or defective operational status of the register

A method for providing redundant registers in a microprocessor of a data processing system, comprising the steps of:

• providing a microprocessor including a predetermined number of registers for storing information;
• identifying each of said predetermined number of registers as having a functional or defective operational status by testing each of said registers to determine a corresponding said operational status;
• storing by a plurality of indicators corresponding to each of said predetermined number of registers said operational status relative to each of said predetermined number of registers;
• generating a bit vector having a plurality of fields each having one of said plurality of indicators stored therein which correspond to each of said predetermined number of registers;
• providing said plurality of indicators to rename logic;
• assigning, by said rename logic in said microprocessor, specific ones of said registers, having a particular operational status, to instructions being processed by said microprocessor;
• and
• activating at least one fuse, which corresponds to one of said plurality of fields, to cause a value in said plurality of fields to be set in accordance with the operational status of a corresponding one of each of said predetermined number of registers.

A microprocessor having redundant registers, comprising:

• a predetermined number of registers, including said redundant registers, for storing information to be used by said microprocessor;
• a test mechanism which determines an operational status of each of said registers and identifies each of said predetermined number of registers as having a functional or defective operational status;
• a plurality of indicators, corresponding to each of said predetermined number of registers, that stores said operational status relative to each of said registers;
• and
• rename logic that assigns specific ones of said predetermined number of registers, having a particular operational status, to instructions being processed by said microprocessor;
• wherein said plurality of indicators comprises a bit vector having a plurality of fields each having one of said plurality of indicators stored therein which correspond to each of said predetermined number of registers;
• and
• wherein said test mechanism includes a set of fuses each corresponding to one of said plurality of fields for causing a value in said plurality of fields to be set in accordance with the operational status of a corresponding one of each of said predetermined number of registers.

A data processing system, comprising:

• a microprocessor including a predetermined number of registers for storing information;
• a test mechanism which determines a functional or defective operational status of each of said predetermined number of registers;
• a bit vector having a plurality of fields corresponding to each of said predetermined number of registers, each of said fields having an indicator representative of said operational status relative to each of said predetermined number of registers;
• and
• rename logic that receives said bit vector and assigns specific ones of said predetermined number of registers, having a functional operational status, to instructions being processed by said microprocessor;
• wherein said predetermined number of registers includes redundant registers such that a sufficient number of registers having a functional operational status will be available for assignment to said instructions by said rename logic when a portion of said predetermined number of registers have a defective operational status;
• and
• wherein said test mechanism activates fuses corresponding to one of said plurality of fields and causes said indicator value in said plurality of fields to be set in accordance with the operational status of a corresponding one of said predetermined number of registers.

A data processing system, comprising:

• a microprocessor including a predetermined number of registers for storing information;
• means for identifying an operational status of each of said predetermined number of registers including a plurality of indicators and a bit vector having a plurality of fields each having one of said plurality of indicators stored therein, said indicators corresponding to each of said predetermined number of registers and store said operational status relative to each of said predetermined number of registers, said means for identifying having a set of fuses each corresponding to one of said plurality of fields for causing a value in said plurality of fields to be set in accordance with the operational status of a corresponding one of each of said predetermined number of registers;
• and
• rename logic that assigns, based on said plurality of indicators, specific ones of said registers having a particular operational status to instructions being processed by said microprocessor.

A method for providing redundant registers in a microprocessor of a data processing system, comprising the steps of:

• providing a microprocessor including a predetermined number of registers for storing information;
• identifying an operational status of each of said predetermined number of registers and storing a plurality of indicators, corresponding to each of said predetermined number of registers, in a one of a plurality of fields included in a bit vector, each said field corresponding to one of said predetermined number of registers, said step of identifying includes activating at least one fuse corresponding to one of said plurality of fields to cause a value in said plurality of fields to be set in accordance with the operational status of a corresponding one of each of said predetermined registers;
• and
• assigning, based on said plurality of indicators, by rename logic in said microprocessor specific ones of said registers having a particular operational status to instructions being processed by said microprocessor.

A microprocessor having redundant registers, comprising:

• a predetermined number of registers, including said redundant registers, for storing information to be used by said microprocessor;
• means for identifying an operational status of each of said predetermined number of registers including a test mechanism which determines said operational status of each of said plurality of registers and a plurality of indicators, corresponding to each of said predetermined number of registers, for storing said operational status relative to each of said predetermined number of registers;
• and
• rename logic that assigns, based on said plurality of indicators, specific ones of said predetermined number of registers, having a particular operational status, to instructions being processed by said microprocessor;
• wherein said means for identifying further comprises a set of fuses, each corresponding to one of a plurality of fields in a bit vector, that cause a value in at least one of said plurality of fields to be set in accordance with the operational status of a corresponding one of each of said predetermined number of registers.

A data processing system, comprising:

• a microprocessor including a predetermined number of registers for storing information;
• a test mechanism which determines an operational status of each of said predetermined number of registers;
• a bit vector having a plurality of fields corresponding to each of said predetermined number of registers, each of said fields having an indicator representative of said operational status relative to each of said predetermined number of registers;
• and
• rename logic that receives said bit vector and assigns specific ones of said predetermined number of registers, having a functional operational status, to instructions being processed by said microprocessor;
• wherein said test mechanism activates fuses corresponding to one of said plurality of fields and causes said indicator in said plurality of fields to be set in accordance with the functional or defective operational status of a corresponding one of said predetermined number of registers;
• and
• wherein said predetermined number of registers includes redundant registers such that a sufficient number of registers having a functional operational status will be available for assignment to said instructions by said rename logic when a portion of said predetermined number of registers have a defective operational status.