Multi-level multiprocessor speculation mechanism

A data processing system comprising:

• a memory system and an interconnect;
• a processor that processes a group of memory access requests that precede a barrier instruction in an instruction sequence;
• and
• a controller, which in response to a determination that all of said memory access requests hit in a cache of said processor, withholds placing a barrier operation associated with said barrier instruction on said interconnect and directs said processor to ignore said barrier instruction and complete processing of a next group of memory access requests following said barrier instruction in said instruction sequence without having to wait until receiving an acknowledgment of a completion of a barrier operation corresponding to said barrier instruction.

A processor comprising:

• an instruction sequencing unit;
• a load store unit (LSU) that issues a group of memory access requests that precede a barrier instruction in an instruction sequence;
• and
• a controller, which in response to a determination that all of said memory access requests hit in a cache affiliated with said processor, withholds issuing on an interconnect a barrier operation associated with said barrier instruction and directs said load store unit to ignore said barrier instruction and complete processing of a next group of memory access requests following said barrier instruction in said instruction sequence without receiving an acknowledgment.