Method and apparatus for instruction set architecture to perform primary and shadow digital signal processing sub-instructions simultaneously

A signal processor for performing digital signal processing instructions, the signal processor comprising:

• at least one signal processing unit including,
• a primary stage to execute a primary digital signal processing sub-instruction of a single digital signal processing instruction based upon current data, the primary digital processing sub-instruction being a dyadic instruction having a primary main operation and a primary sub operation;
• and
• a shadow stage to simultaneously execute a shadow digital signal processing sub-instruction of the single digital signal processing instruction based upon delayed data;
• wherein, the primary main operation of the primary digital signal processing sub-instruction is one of the set of multiplication, addition, comparison with a minimum or maximum value, and no operation.

A signal processor for performing digital signal processing instructions, the signal processor comprising:

• at least one signal processing unit including,
• a primary stage to execute a primary digital signal processing sub-instruction of a single digital signal processing instruction based upon current data, the primary digital processing sub-instruction being a dyadic instruction having a primary main operation and a primary sub operation;
• and
• a shadow stage to simultaneously execute a shadow digital signal processing sub-instruction of the single digital signal processing instruction based upon delayed data;
• wherein,
• the shadow digital signal processing sub-instruction is a dyadic instruction having a shadow main operation and a shadow sub operation;
• and
• the shadow main operation of the shadow digital signal processing sub-instruction is one of the set of multiplication, addition, comparison with a minimum or maximum value, and no operation.

A signal processor for performing digital signal processing instructions, the signal processor comprising:

• at least one signal processing unit including,
• a primary stage to execute a primary digital signal processing sub-instruction of a single digital signal processing instruction based upon current data, the primary digital processing sub-instruction being a dyadic instruction having a primary main operation and a primary sub operation;
• and
• a shadow stage to simultaneously execute a shadow digital signal processing sub-instruction of the single digital signal processing instruction based upon delayed data;
• a host interface to interface to an external host computer;
• an external memory interface to read and write data to an external memory;
• clock and phase-locked loop to control the timing of operations of the application specific signal processor;
• and
• a memory movement engine coupled to the buffer memory to transceive data thereto and therefrom;
• and
• wherein the at least one signal processing unit further includes,
• a data typer and aligner to order the bits of the operands for execution, a third adder to add operands together, and a compressor to compress more than two operands into a pair of operands.

A method of performing digital signal processing (DSP) instructions in a signal processor, the method comprising:

• executing a single DSP instruction having a primary DSP sub-instruction and a shadow DSP sub-instruction;
• selecting delayed data based upon the shadow sub-DSP instruction;
• storing the delayed data;
• and
• executing the primary DSP sub-instruction within a primary stage of a signal processing unit based upon current data and simultaneously executing the shadow DSP sub-instruction within a shadow stage of the signal processing unit based upon the delayed data;
• wherein,
• the signal processor comprises a plurality of signal processing units, each signal processing unit having a plurality of delayed data registers to store the delayed data and a shadow selector coupled to each of the delayed data registers, further comprising,
• selecting delayed data from the delayed data registers of the signal processing units for use by the shadow stages of the signal processing units;
• and
• controlling the selection of the delayed data based upon the shadow DSP sub-instruction for use by the shadow stages of the signal processing units.