Parallel processor and image processing system for simultaneous processing of plural image data items without additional circuit delays and power increases

An image processing system configured to input image data, operate to parallel process said image data, and output processed data to an external unit, comprising:

• a parallel processor comprising a plurality of processor elements provided to form an array for said image data to be input;
• and
• a FIFO memory to perform at least one of an inputting operation of said image data and an outputting operation of said processed data to said external unit, by way thereof,
• wherein
• each of said processor elements comprises a plurality of functional means including at least an operation unit and a register file provided with a plurality of registers,
• each of said functional means is connected to an internal bus,
• a transfer and an exchange of data among said functional means are carried out by way of said internal bus,
• an operation of said functional means is controlled by a logic of global control signals generated by said global processor,
• said processor elements are divided into groups each including an arbitrary number thereof,
• buffer means to buffer said control signals is provided in each of said groups,
• said global control signals are input into said buffer means,
• local control signals are generated by said buffer means,
• said local control signals are sent to each of said groups to be subsequently terminated within said each of said groups,
• said global control signals are provided to all of said buffer means in said groups, and
• said processed data are output to said external unit in response to said global control signals.

A method for inputting image data, operating to parallel process said image data, and outputting processed data to an external unit, for an image processing system, comprising the steps of:

• inputting said image data into a parallel processor comprising a plurality of processor elements provided forming an array;
• performing at least one of inputting operation of said image data and an outputting operation of said processed data to said external unit, by way a FIFO memory;
• wherein
• each of said processor elements comprises a plurality of functional means including at least an operation unit and a register file provided with a plurality of registers,
• each of said functional means is connected to an internal bus,
• a transfer and an exchange of data among said functional means are carried out by way of said internal bus,
• an operation of said functional means is controlled by a logic of global control signals generated by said global processor,
• said processor elements are divided into groups each including an arbitrary number thereof,
• buffer means to buffer said control signals is provided in each of said groups,
• said global control signals are input into said buffer means,
• local control signals are generated by said buffer means,
• said local control signals are sent to each of said groups to be subsequently terminated within said each of said groups,
• said global control signals are provided to all of said buffer means in said groups, and
• said processed data are output to said external unit in response to said global control signals.

A parallel processor comprising:

• global processor means for decoding programs and assuming overall control of said parallel processor;
• and
• processor element block means comprising a plurality of processor element means for processing various data,
• wherein
• each of said processor element means comprises a plurality of functional means including at least an operation unit and register file provided with a plurality of registers,
• each of said functional means is connected to an internal bus,
• an operation of said functional means is controlled by a logic of global control signals generated by said global processor,
• said processor elements are divided into groups each including an arbitrary number thereof,
• buffer means to buffer said control signals is provided in each of said groups,
• said global control signals are input into said buffer means,
• local control signals are generated by said buffer means,
• said local control signals are sent to each of said groups to be subsequently terminated within each of said groups, and
• said global control signals are provided to all of said buffer means in said groups.

An image processing system configured to input image data, operate to parallel process said image data, and output processed data to external means, comprising:

• parallel processor means comprising a plurality of processor elements provided forming array means for said image data to be input;
• and
• FIFO memory means for performing at least one of an inputting operation of said image data and an outputting operation of said processed data to said external means, by way thereof,
• wherein
• each of said processor elements comprises a plurality of functional means including at least an operation unit and a register file provided with a plurality of registers,
• each of said functional means is connected to an internal bus,
• a transfer and an exchange of data among said functional means are carried out by way of said internal bus,
• an operation of said functional means is controlled by a logic of global control signals generated by said global processor,
• said processor elements are divided into groups each including an arbitrary number thereof,
• buffer means to buffer said control signals is provided in each of said groups,
• said global control signals are input into said buffer means,
• local control signals are generated by said buffer means,
• said local control signals are sent to each of said groups to be subsequently terminated within each of said groups,
• said global control signals are provided to all of said buffer means in said groups, and
• said processed data are output to said external unit means in response to said global control signals.