Method and apparatus for a low latency source-synchronous address receiver for a host system bus in a memory controller

An address receiver, comprising:

• a flow-through circuit to generate an enable signal in response to a digital address strobe signal and a digital address select signal to activate the enable signal prior to receipt of an address packet;
• an input differential amplifier to compare an address packet received on an address pin for a data request against a reference voltage and generate a digital address packet, the digital address packet having a first component describing a transaction type of the address packet and a second component describing attributes of the address packet;
• a flow-through gate having the digital address packet and the enable signal as inputs, the flow-through gate providing the first component of the digital address packet to a chipset in response to the enable signal once the digital address packet appears on the address pin, thereby providing a flow through path from the address pin to the chipset for the first component of the digital address packet to expedite initiation of decoding of the address packet by the chipset;
• and
• a non flow-through gate having the digital address packet and a digital address strobe signal as inputs and providing the second component of the digital address packet to the chipset in response to the digital address strobe signal, such that the chipset can complete decoding of the address packet.

A memory controller comprising:

• a chipset coupled to the memory by a memory bus;
• a system bus coupling a processor to the chipset, the chipset decoding an address packet on the system bus for data requested by the processor from the memory, wherein the system bus includes a source-synchronous address receiver including:
• a flow-through circuit to generate an enable signal in response to a digital address strobe signal and a digital address select signal to activate the enable signal prior to receipt of an address packet;
• a flow-through gate having the digital address packet and the enable signal as inputs, the flow-through gate to provide the first component of the digital address packet to a chipset in response to the enable signal once the digital address packet appears on an address pin, thereby providing a flow-through path from the address pin to the chipset for the first component of the digital address packet to expedite initiation of decoding of the address packet by the chipset;
• and
• a non flow-through gate having the digital address packet and the digital address strobe signal as inputs and providing the second component of the digital address packet to the chipset in response to the digital address strobe signal, such that the chipset can complete decoding of the address packet.