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US 6,748,512 B2Granted
Method and apparatus for mapping address space of integrated programmable devices within host system memory
AssigneeIntel Corporation
InventorsDeep Buch, Varghese George, Vladimir Pentkovski, Paul Zagacki, Edward Gamsaragan
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Abstract
A Method and Apparatus for Mapping Address Space of Integrated Programmable Devices within Host System Memory is described herein.
Claims37
A method Comprising:
- mapping at least one address originating from a programmable device within a computer system to a portion of system memory, said mapping using an Extended Address Re-mapping Table (XART);
- maintaining coherency within at least one CPU cache, said maintaining coherency comprising snooping only addresses not originating from said programmable device.
A method comprising:
- mapping at least one address originating from any of a plurality of programmable devices within a computer system to system memory, said mapping using an Extended Address Re-mapping Table (XART);
- maintaining coherency within at least one CPU cache, said maintaining coherency comprising snooping only addresses not originating from said any of a plurality of programmable devices.
An apparatus comprising:
- a unit to map at least one address originating from any of a plurality of programmable devices within a computer system to system memory, said mapping using an Extended Address Re-mapping Table (XART);
- a unit to maintain coherency within at least one CPU cache, said
- maintaining coherency comprising snooping only addresses not originating from said any of a plurality of programmable devices.
A system comprising:
- at least one microprocessor, said microprocessor comprising at least one CPU core, at least one virtual PCI-to-PCI bridge circuit (VPBC), and at least one co-processor coupled to said at least one CPU core by said at least one VPBC;
- at least one bridge coupled to said at least one microprocessor and said at least one VPBC;
- a system memory coupled to said at least one bridge;
- wherein said at least one co-processor is configured as a PCI device;
- and
- wherein said at least one VPBC, and said at least one co-processor are integrated within the same substrate as said at least one CPU core.
3 more elements
A computer-readable medium having stored thereon a set of instructions to translate instructions, said set of instructions, which when executed by a processor, cause said processor to perform a method comprising:
- mapping at least one address originating from any of a plurality of programmable devices within a computer system to system memory, said mapping using an Extended Address Re-mapping Table (XART);
- maintaining coherency within at least one CPU cache, said maintaining coherency comprising snooping only addresses not originating from said any of a plurality of programmable devices.
Dependencies are inferred from the claim text.