Memory component with configurable multiple transfer formats

A memory component for coupling via external interconnect to an external controller such as a memory controller, the controller generating requests, the memory component performing information transfers with the external controller in response to at least some of the requests, the memory component comprising:

• a single integrated circuit, including:
• (i) a plurality of connections coupling the integrated circuit to the external interconnect;
• (ii) a storage subsystem having a plurality of addressable storage locations, each addressable storage location comprising a respective group of at least one bit of storage, the storage subsystem being coupled to at least some of the connections;
• (iii) a plurality of configuration bits in at least one configuration register, the register being coupled to at least some of the connections, the configuration bits being programmable by at least one of the requests, the configuration bits specifying at least one of a plurality of modes of operation, the modes of operation including transfer modes wherein at least some of the information transfers have a length corresponding to a mode-specific number of the addressable storage locations;
• and
• (iv) control logic coupled to the storage subsystem, the configuration bits, and at least some of the connections, the control logic generating information transfer control signals as specified by the requests and the configuration bits.

A memory component for coupling via external interconnect to an external controller such as a memory controller, the controller generating requests, the memory component performing information transfers with the external controller in response to at least some of the requests, the memory component comprising:

• a single integrated circuit, including:
• (i) a plurality of connections coupling the integrated circuit to the external interconnect, the plurality of connections including a first connection group conveying at least one externally provided timing signal having a frequency of at least 100 MHz and a second connection group conveying at least part of the information transfers via at least one information transfer signal, the information transfer signal being synchronous with the externally provided timing signal during at least a first interval of time;
• (ii) a storage subsystem having a plurality of addressable storage locations, each addressable storage location being randomly accessible and comprising a respective group of at least one bit of dynamic storage, the storage subsystem being coupled to at least some of the connections;
• (iii) a plurality of configuration bits in at least one configuration register, the register being coupled to at least some of the connections, the configuration bits being programmable by at least one of the requests, the configuration bits specifying at least one of a plurality of modes of operation, the modes of operation including transfer modes wherein the information transfer length corresponds to a mode-specific number of the addressable storage locations, the number of the mode-specific information transfer lengths being less than the length of the maximum information transfer length, at least one of the transfer modes specifying an information transfer of 4 addressable storage locations, the transfer mode specified by the configuration bits being persistent across multiple information transfers commanded by the requests;
• and
• (iv) control logic coupled to the storage subsystem, the configuration bits, and at least some of the connections, the control logic generating information transfer control signals only as specified by the requests and the configuration bits, the configuration bits having been written by a previous request.

A memory component for coupling via external interconnect to an external controller such as a memory controller, the controller generating rates requests, the memory component performing information transfers with the external controller in response to at least some of the requests, the memory component comprising:

• a single integrated circuit, including:
• (i) a plurality of connections coupling the integrated circuit to the external interconnect, the plurality of connections including a first connection group conveying at least two externally provided timing signals each having a frequency of at least 100 MHz and a second connection group conveying at least part of the information transfers via at least one information transfer signal, the information transfer signal being synchronous with at least one of the externally provided timing signals during at least a first interval of time;
• (ii) a storage subsystem having a plurality of addressable storage locations, each addressable storage location being randomly accessible and comprising a respective group of at least one bit of dynamic storage, the storage subsystem being coupled to at least some of the connections;
• (iii) a plurality of configuration bits in at least one configuration register, the register being coupled to at least some of the connections, the configuration bits being programmable by at least one of the requests, the configuration bits specifying at least one of a plurality of modes of operation, the modes of operation including transfer modes wherein the information transfer length corresponds to a mode-specific number of the addressable storage locations, the number of the mode-specific information transfer lengths being less than the length of the maximum information transfer length, at least one of the transfer modes specifying an information transfer of 4 addressable storage locations, the transfer mode specified by the configuration bits being persistent across multiple information transfers commanded by the requests;
• and
• (iv) control logic coupled to the storage subsystem, the configuration bits, and at least some of the connections, the control logic generating information transfer control signals only as specified by the requests and the configuration bits, the configuration bits having been written by a previous request.

A memory component for coupling via external interconnect to an external controller such as a memory controller, the controller generating requests, the memory component performing data transfers with the external controller in response to at least some of the requests, the memory component comprising:

• a single integrated circuit, including:
• (i) a plurality of connections coupling the integrated circuit to the external interconnect, the plurality of connections including a first connection group conveying at least one externally provided timing signal having a frequency of at least 100 MHz and a second connection group conveying at least part of the data transfers via at least eight data transfer signals, the data transfer signals being synchronous with the externally provided timing signal during at least a first interval of time;
• (ii) a storage subsystem having a plurality of addressable storage locations, each addressable storage location being randomly accessible and comprising a respective group of at least eight bits of dynamic storage, the storage subsystem being coupled to at least some of the connections;
• (iii) a plurality of configuration bits in at least one configuration register, the register being coupled to at least some of the connections, the configuration bits being programmable by at least one of the requests, the configuration bits specifying at least one of a plurality of modes of operation, the modes of operation including transfer modes wherein the data transfer length corresponds to a mode-specific number of the addressable storage locations, the number of the mode-specific data transfer lengths being less than the length of the maximum data transfer length, at least one of the transfer modes specifying a data transfer of 4 addressable storage locations, the transfer mode specified by the configuration bits being persistent across multiple data transfers commanded by the requests;
• and
• (iv) control logic coupled to the storage subsystem, the configuration bits, and at least some of the connections, the control logic generating data transfer control signals only as specified by the requests and the configuration bits, the configuration bits having been written by a previous request.

A memory component for coupling via external interconnect to an external controller such as a memory controller, the controller generating requests, the memory component performing data transfers with the external controller in response to at least some of the requests, the memory component comprising:

• a single integrated circuit, including:
• (i) a plurality of connections coupling the integrated circuit to the external interconnect, the plurality of connections including a first connection group conveying at least two externally provided timing signals each having a frequency of at least 100 MHz, and a second connection group conveying at least part of the data transfers via at least eight data transfer signals, the data transfer signals being synchronous with at least one of the externally provided timing signals during at least a first interval of time;
• (ii) a storage subsystem having a plurality of addressable storage locations, each addressable storage location being randomly accessible and comprising a respective group of at least eight bits of dynamic storage, the storage subsystem being coupled to at least some of the connections;
• (iii) a plurality of configuration bits in at least one configuration register, the register being coupled to at least some of the connections, the configuration bits being programmable by at least one of the requests, the configuration bits specifying at least one of a plurality of modes of operation, the modes of operation including transfer modes wherein the data transfer length corresponds to a mode-specific number of the addressable storage locations, the number of the mode-specific data transfer lengths being less than the length of the maximum data transfer length, at least one of the transfer modes specifying a data transfer of 4 addressable storage locations, the transfer mode specified by the configuration bits being persistent across multiple data transfers commanded by the requests;
• and
• (iv) control logic coupled to the storage subsystem, the configuration bits, and at least some of the connections, the control logic generating data transfer control signals only as specified by the requests and the configuration bits, the configuration bits having been written by a previous request.

A memory component for performing information transfers in response to requests by an external controller such as a memory controller, the controller being coupled to the memory component via external interconnect, the information transfers being between the external controller and the memory component, the memory component comprising:

• a single integrated circuit, including:
• (i) a plurality of connections coupling the integrated circuit to the external interconnect;
• (ii) a storage subsystem having a plurality of addressable storage locations, each addressable storage location comprising a respective group of at least one bit of storage, each bit of storage having an associated bit of information, the storage subsystem being coupled to a subset of the connections;
• (iii) a plurality of configuration bits in at least one configuration register, the register being coupled to at least some of the connections, the configuration bits being programmable by at least some of the information transfers via at least some of the plurality of connections, the configuration bits specifying at least one of a plurality of modes of operation, the at least one mode of operation specified by the configuration bits being persistent across multiple information transfers commanded by the requests;
• and
• (iv) control logic coupled to the storage subsystem and the configuration bits, the control logic asserting information transfer control signals as specified by the information transfer requests and the configuration bits, at least some of the bits of storage participating in at least some of the information transfers, the values of the associated bits of information being preserved between the participating bits of storage and the subset of the connections,
• wherein a first connection group within the plurality of connections conveys at least one externally provided timing signal having a frequency of at least 100 MHz, a second connection group within the plurality of connections conveys at least one information signal, and wherein the integrated circuit further includes a storage element having a data input coupled to the information signal and a clock input coupled to the externally provided timing signal,
• wherein the storage element is an element in a register, and
• wherein the register is a shift-register.

A memory component for performing information transfers in response to requests by an external controller such as a memory controller, the controller being coupled to the memory component via external interconnect, the information transfers being between the external controller and the memory component, the memory component comprising:

• a single integrated circuit, including:
• (i) a plurality of connections coupling the integrated circuit to the external interconnect;
• (ii) a storage subsystem having a plurality of addressable storage locations, each addressable storage location comprising a respective group of at least one bit of storage, each bit of storage having an associated bit of information, the storage subsystem being coupled to a subset of the connections;
• (iii) a plurality of configuration bits in at least one configuration register, the register being coupled to at least some of the connections, the configuration bits being programmable by at least some of the information transfers via at least some of the plurality of connections, the configuration bits specifying at least one of a plurality of modes of operation, the at least one mode of operation specified by the configuration bits being persistent across multiple information transfers commanded by the requests;
• and
• (iv) control logic coupled to the storage subsystem and the configuration bits, the control logic asserting information transfer control signals as specified by the information transfer requests and the configuration bits, at least some of the bits of storage participating in at least some of the information transfers, the values of the associated bits of information being preserved between the participating bits of storage and the subset of the connections,
• wherein the integrated circuit further includes at least eight shift registers, and the plurality of connections includes a first group of at least eight connections conveying information signals, the information signals being coupled to the respective shift registers.

A memory component for performing information transfers in response to requests by an external controller such as a memory controller, the controller being coupled to the memory component via external interconnect, the information transfers being between the external controller and the memory component, the memory component comprising:

• a single integrated circuit, including:
• (i) a plurality of connections coupling the integrated circuit to the external interconnect;
• (ii) a storage subsystem having a plurality of addressable storage locations, each addressable storage location comprising a respective group of at least one bit of storage, each bit of storage having an associated bit of information, the storage subsystem being coupled to a subset of the connections;
• (iii) a plurality of configuration bits in at least one configuration register, the register being coupled to at least some of the connections, the configuration bits being programmable by at least some of the information transfers via at least some of the plurality of connections, the configuration bits specifying at least one of a plurality of modes of operation, the at least one mode of operation specified by the configuration bits being persistent across multiple information transfers commanded by the requests;
• and
• (iv) control logic coupled to the storage subsystem and the configuration bits, the control logic asserting information transfer control signals as specified by the information transfer requests and the configuration bits, at least some of the bits of storage participating in at least some of the information transfers, the values of the associated bits of information being preserved between the participating bits of storage and the subset of the connections,
• wherein the integrated circuit further includes at least twelve shift registers, and the plurality of connections includes a first group of at least twelve connections conveying information signals, the information signals being coupled to the respective shift registers.

A method of memory operation comprising:

• (a) providing a single-chip dynamic random access memory having at least one configuration register and a plurality of chip interface connections in at least a first and a second connection group, each connection group having at least one connection;
• (b) receiving at least one timing signal via the first connection group, the timing signal having a frequency of at least 100 MHz;
• (c) receiving transfer length mode information via at least some of the connections of the second connection group;
• (d) storing the transfer length mode information in the configuration register;
• (e) receiving an information transfer request via at least some of the connections of the second connection group;
• (f) executing the information transfer request in accordance with the information transfer request and at least some of the stored transfer length mode information;
• and
• (g) maintaining the transfer length mode information in the configuration register subsequent to the execution of the information transfer request.

A method of memory operation comprising:

• (a) providing a single-chip dynamic random access memory having at least one configuration register and a plurality of chip interface connections in at least a first and a second connection group, each connection group having at least one connection;
• (b) receiving at least one timing signal via the first connection group, the timing signal having a frequency of at least 100 MHz;
• (c) receiving mode information via at least some of the connections of the second connection group, the mode information including information transfer length information
• (d) storing the transfer length mode information in the configuration register;
• (e) receiving an information transfer request via at least some of the connections of the second connection group;
• (f) transferring data via at least some of the connections of the second connection group, the transferring being performed synchronously with the timing signal and in accordance with the information transfer request and at least some of the stored transfer length mode information;
• and
• (g) maintaining the transfer length mode information in the configuration register subsequent to the execution of the information transfer request.

A method of memory operation comprising:

• (a) providing a single-chip dynamic random access memory having at least one configuration register and a plurality of chip interface connections in at least a first and a second connection group, the second connection group having at least one connection;
• (b) receiving at least two timing signals via the first connection group, each of the timing signals having a frequency of at least 100 MHz;
• (c) receiving transfer length mode information via at least some of the connections of the second connection group;
• (d) storing the transfer length mode information in the configuration register;
• (e) receiving an information transfer request via at least some of the connections of the second connection group;
• (f) executing the information transfer request in accordance with the information transfer request and at least some of the stored transfer length mode information;
• and
• (g) maintaining the transfer length mode information in the configuration register subsequent to the execution of the information transfer request.

A method of using a single-chip dynamic random access memory, the method comprising:

• (a) coupling the single-chip memory to an external controller;
• (b) providing at least one timing signal having a frequency of at least 100 MHz to the single-chip memory;
• (c) transferring transfer length mode information from the external controller to the single-chip memory;
• (d) storing the transfer length mode information in at least one configuration register in the single-chip memory;
• (e) receiving an information transfer request from the external controller subsequent to the storing of the transfer length mode information;
• and
• (f) the single-chip memory responding to the information transfer request from the external controller according to the received information transfer request and at least some of the stored transfer length mode information;
• and
• (g) maintaining the transfer length mode information subsequent to the responding to the information transfer request.

A method of using a single-chip dynamic random access memory, the method comprising:

• (a) coupling the single-chip memory to an external controller;
• (b) providing at least one timing signal having a frequency of at least 100 MHz to the single-chip memory;
• (c) transferring transfer length mode information from the external controller to the single-chip memory;
• (d) storing the transfer length mode information in at least one configuration register in the single-chip memory;
• (e) receiving an information transfer request from the external controller subsequent to the storing of the transfer length mode information;
• (f) transferring data synchronously with the timing signal according to the information transfer request, the amount of data transferred being indicated by at least some of the stored transfer length mode information;
• and
• (g) maintaining the transfer length mode information subsequent to the transferring of the data.

A method of using a single-chip dynamic random access memory, the method comprising:

• (a) coupling the single-chip memory to an external controller;
• (b) providing at least two timing signals each having a frequency of at least 100 MHz to the single-chip memory;
• (c) transferring transfer length mode information from the external controller to the single-chip memory;
• (d) storing the transfer length mode information in at least one configuration register in the single-chip memory;
• (e) receiving an information transfer request from the external controller subsequent to the storing of the transfer length mode information;
• (f) the single-chip memory responding to the information transfer request from the external controller according to the information transfer request and at least some of the stored transfer length mode information;
• and
• (g) maintaining the transfer length mode information subsequent to the responding to the information transfer request.