US 6,748,507 B2 · Single-chip microcomputer with integral clock generating unit providing clock signals to CPU, internal circuit modules and synchronously controlling external dynamic memory

Abstract

A single-chip microcomputer comprising: a first bus having a central processing unit and a cache memory connected therewith; a second bus having a dynamic memory access control circuit and an external bus interface connected therewith; a break controller for connecting the first bus and the second bus selectively; a third bus having a peripheral module connected therewith and having a lower-speed bus cycle than the bus cycles of the first and second buses; and a bus state controller for effecting a data transfer and a synchronization between the second bus and the third bus. The single-chip microcomputer has the three divided internal buses to reduce the load capacity upon the signal transmission paths so that the signal transmission can be accomplished at a high speed. Moreover, the peripheral module required to have no operation speed is isolated so that the power dissipation can be reduced.

Claims3

Dependent claims

A single-chip microcomputer for use with an external synchronous dynamic memory, wherein the external synchronous dynamic memory includes a clock signal input terminal and a chip select signal input terminal, the single-chip microcomputer comprising:

a central processing unit;
a clock generating unit for use with an external oscillator, and including a PLL;
a control unit coupled to the central processing unit via an internal bus, and including a register;
a first external terminal;
and
a second external terminal,
wherein the clock generating unit generates a first clock signal and a second clock signal,
wherein the second clock signal is provided to the central processing unit,
wherein the first clock signal is provided to the clock signal input terminal of the external synchronous dynamic memory via the first external terminal, and
wherein the control unit provides a chip select signal to the chip select signal input terminal of the external synchronous dynamic memory via the second external terminal.

7 more elements

Dependencies are inferred from the claim text.

Facts

Application

10/172,290Filed 13 Jun 2002 · continuation

Priority

JP 5-25509917 Sep 1993

Published

US 2003/0046514 A16 Mar 2003

Granted

8 Jun 2004

Term ends

Not estimatedThe source records don’t support an estimate.

Classification12 codes

G06F 9/3001
To perform operations on data operands: arithmetic instructions
G06F 12/0893
Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches: caches…
G06F 13/36
Handling requests for interconnection or transfer: for access to common bus or bus system
G06F 13/405
Using bus bridges: where the bridge performs a synchronising function

Family

Application08/306,100Parent of this continuation · filed 14 Sep 1994

Application09/055,099Parent of this continuation · filed 3 Apr 1998

Application09/191,313Parent of this continuation · filed 13 Nov 1998

Application09/467,087Parent of this continuation · filed 10 Dec 1999

Application09/918,625Parent of this continuation · filed 30 Jul 2001

US 2003/0046514 A1Pre-grant publication · published 6 Mar 2003

US 6,591,294 B2Parent of this continuation

US 6,279,063 B1Parent of this continuation

US 6,212,620 B1Parent of this continuation

US 5,930,523 AParent of this continuation

US 2002/0007430 A1Published application

US 6,748,507 B2This patent

From the US filing history. Foreign family members aren’t listed.

Single-chip microcomputer with integral clock generating unit providing clock signals to CPU, internal circuit modules and synchronously controlling external dynamic memory

Life of this patent

Single-chip microcomputer with integral clock generating unit providing clock signals to CPU, internal circuit modules and synchronously controlling external dynamic memory

Life of this patent

Abstract

Claims3