US 6,748,505 B1 · Efficient system bus architecture for memory and register transfers

Abstract

A method of efficiently performing transactions on the system bus which includes at least a request signal line, a grant signal line, a set of address signal lines, and a set of data signal lines in which upon the falling edge of the grant signal from the memory controller for a first memory transaction and prior to the completion of the servicing of the first memory transaction, a second memory transaction can be issued. Once a first address corresponding to the first memory transaction request is transmitted to the memory controller, the address lines are available for transmitting a second address corresponding to the second memory transaction request to the memory controller. The memory controller then stores the second address in a buffer whereupon the completion of servicing the first memory transaction request, the second request can be serviced without waiting for the second request arbitration process or for the address to be transmitted to the memory controller. In addition, in another aspect of the method for efficiently utilizing the system bus, register transactions between system sub-blocks and the system's central processing unit are performed using the system bus by multiplexing register data onto the address signal lines of the system bus when the address signal lines are idle, thereby further minimizing address line idle cycles.

Claims101

Dependent claims

A method of performing memory transactions in a processing system including a plurality of system sub-blocks, a memory controller, a main memory, and a system bus including a first set of signal lines for transmitting memory transaction request and grant signals, a second set of signal lines for transmitting memory transaction address signals, and a third set of signal lines for transmitting memory transaction data signals, said method comprising the steps of:

1) a first sub-block transmitting a first memory transaction request signal on said first set of signal lines to said memory controller for performing a first memory transaction with said main memory;
2) said memory controller issuing a first grant signal on said first set of signal lines to said first sub-block in response to said first memory transaction request signal;
3) said first sub-block transmitting a first address corresponding to said first memory transaction;
4) said memory controller servicing said first memory transaction request upon receipt of said first address;
wherein after said issuing of said first grant signal (step 2) and prior to completion of said servicing of said first memory transaction (step 4):
a) said memory controller issuing a second grant signal, based upon an arbitration scheme in response to a second memory transaction request signal originating from one of said plurality of system sub-blocks;
and
b) said one system sub-block transmitting a second address corresponding to said second memory transaction to said memory controller;
c) storing said second address in said memory controller;
d) said memory controller accessing said second address on completion of said servicing of said first memory transaction request;
and
e) servicing said second memory transaction request.

9 more elements

Dependencies are inferred from the claim text.

Efficient system bus architecture for memory and register transfers

Life of this patent

Efficient system bus architecture for memory and register transfers

Life of this patent

Abstract

Claims101