US 6,748,498 B2Granted

Scalable multiprocessor system and cache coherence method implementing store-conditional memory transactions while an associated directory entry is encoded as a coarse bit vector

AssigneeHewlett-Packard Development Company, L.P.

InventorsKourosh Gharachorloo, Luiz Andre Barroso, Mosur K. Ravishankar, Robert J. Stets, Daniel J. Scales

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Abstract

A system including a plurality of processor nodes is configured to execute a cache coherence protocol that avoids the use of negative acknowledgments and ordering requirements on the underlying transaction-message interconnect/network, and implements store-conditional memory transactions. A store-conditional memory transaction succeeds if a directory tracking the state of a memory line of information unambiguously indicates that the requesting node is the exclusive owner of the memory line, if the directory ambiguously indicates that the requesting node is sharing the memory line and the requesting node is in fact sharing the memory line, or if the directory unambiguously indicates that the requesting node is sharing the memory line. The store-conditional memory transaction fails if the directory unambiguously indicates that the requesting node is not sharing the memory line, or if the directory ambiguously indicates that the requesting node may be sharing the memory line and the requesting node is in fact not sharing the memory line.

Claims49

Dependent claims

A multiprocessor computer system including a plurality of nodes, each node including:

an interface to a local memory subsystem, the local memory subsystem storing a multiplicity of memory lines of information and a directory;
a memory cache for caching a multiplicity of memory lines of information, including memory lines of information stored in a remote memory subsystem that is local to another node;
a protocol engine implementing a negative acknowledgment free cache coherence protocol, the protocol engine including
a memory transaction array for storing an entry related to a memory transaction, the entry including a memory transaction state, the memory transaction concerning a memory line of information;
and
logic for processing the memory transaction, including advancing the memory transaction when predefined criteria are satisfied and storing a state of the memory transaction in the memory transaction array;
wherein the protocol engine is configured to support a store-conditional memory transaction initiated by a requesting node for exclusive ownership of an identified memory line of information stored in the remote memory subsystem that is local to a first node in the plurality of nodes, and wherein
the store-conditional memory transaction succeeds if the directory in the memory subsystem local to the first node unambiguously indicates that the requesting node is exclusive owner of the memory line of information;
the store-conditional memory transaction succeeds if the directory in the memory subsystem local to the first node unambiguously indicates that the requesting node is sharing the memory line of information;
the store-conditional memory transaction succeeds if the directory in the memory subsystem local to the first node ambiguously indicates that the requesting node is sharing the memory line of information and the requesting node is in fact sharing the memory line of information;
and
the store-conditional memory transaction fails if the directory in the memory subsystem local to the first node unambiguously indicates that the requesting node is not sharing the memory line of information.

9 more elements

A multiprocessor computer system including a plurality of nodes, each node including

an interface to a local memory subsystem, the local memory subsystem storing a multiplicity of memory lines of information and a directory;
a memory cache for caching a multiplicity of memory lines of information, including memory lines of information stored in a remote memory subsystem that is local to another node;
a protocol engine implementing a negative acknowledgment free cache coherence protocol, the protocol engine including
a memory transaction array for storing an entry related to a memory transaction, the entry including a memory transaction state, the memory transaction concerning a memory line;
logic for processing the memory transaction, including advancing the memory transaction when predefined criteria are satisfied and storing a state of the memory transaction in the memory transaction array;
the protocol engine configured to support a store-conditional memory transaction, wherein
the protocol engine included in a requesting node from the plurality of nodes sends a store-conditional request to a first node from the plurality of nodes, said store-conditional request identifying a memory line of information stored in the remote memory subsystem that is local to the first node;
the protocol engine included in the first node sends a may-succeed reply to the requesting node in response to the store-conditional request if the directory in the memory subsystem local to the first node ambiguously indicates that the requesting node is sharing the memory line of information;
the protocol engine included in the requesting node sends a first responsive protocol message to the first node in response to the may-succeed reply if the requesting node is sharing the memory line of information;
and
the protocol engine included in the first node modifies a directory entry, in the directory in the memory subsystem local to the first node, corresponding to the memory line of information to indicate that the requesting node is exclusive owner of the memory line of information in response to the first responsive protocol message.

8 more elements

Dependencies are inferred from the claim text.

Facts

Application: 10/042,053Filed 7 Jan 2002 · continuation in part
Priority: 10 Jun 2000
Published: US 2002/0007443 A15 Sep 2002
Granted: 8 Jun 2004
Term ends: Not estimatedThe source records don’t support an estimate.

Classification6 codes

G06F 12/0826
Using directory methods: limited pointers directories; State-only directories without pointers
G06F 12/0828
Using directory methods: with concurrent directory accessing, i.e. handling multiple concurrent coherency transactions
G06F 2212/621
Details of cache specific to multiprocessor cache arrangements: coherency control relating to peripheral accessing, e.g. from DMA or I/O device
Y10S 707/99952
File or database maintenance: coherency, e.g. same view to multiple users

Family

Application60/210,675Us provisional application · filed 10 Jun 2000
Application09/878,982Parent of this continuation-in-part · filed 11 Jun 2001
US 2002/0124144 A1Pre-grant publication · published 5 Sep 2002
US 2002/0007443 A1Published application
US 6,751,710 B2Related patent
US 6,748,498 B2This patent

From the US filing history. Foreign family members aren’t listed.