Systems and methods for buffering memory transactions

A system comprising:

• a processor configured to decode a digital signal from a digital signal source;
• a memory device for storing instructions and data for said processor, the instructions including instructions for decoding said digital signal;
• a buffer device coupled between said processor and said memory device for buffering memory transactions between said processor and said memory device, said buffer device comprising:
• a read buffer unit configured for storing at least one data value read from a memory device;
• and
• a write buffer unit configured for storing at least one data value for writing to said memory device, wherein said read buffer unit is operable for updating with said at least one data value for writing to said memory device in response to a write to said write buffer unit;
• and
• an amplifier for amplifying a decoded digital signal from said processor.

A memory device transaction method comprising the steps of:

• in response to a transaction request to a write buffer unit:
• if a request address corresponds to a data address in a read buffer unit:
• copying data in the write buffer unit to the read buffer unit;
• and
• locking said read buffer unit.