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US 6,748,490 B1Granted
Method and apparatus for maintaining data coherency in a shared memory system
AssigneeATI International SRL
InventorStephen L. Morein
Life of this patent
Estimating the term…
Abstract
A method and apparatus for ensuring data coherency in a processing system that includes shared memory is presented. This is accomplished by including a hierarchical validity database within the core logic that interconnects the various memory clients to the memory structure. The hierarchical validity database stores a number of hierarchical levels, where each level pertains to different sized portions of the memory. Validity of a portion, or block, within the memory can be determined by referencing the hierarchical validity database.
Claims29
A processing circuit, comprising:
- memory that stores data corresponding to a memory address space wherein the memory is accessed using memory addresses that correspond to the memory address space;
- and
- a core logic block that is operably coupled to the memory, wherein the core logic block receives memory access requests from a plurality of memory clients, wherein the core logic block includes hierarchical validity database that stores indications as to data validity within the memory, wherein the core logic block updates the hierarchical validity database based on at least a portion of memory accesses that affect data coherency within the memory, wherein the core logic block consults the hierarchical validity database to ensure data coherency for memory access requests corresponding to memory read operations.
A processing circuit, comprising:
- memory that stores data corresponding to a memory address space wherein the memory is accessed using memory addresses that correspond to the memory address space;
- and
- a core logic block that is operably coupled to the memory, wherein the core logic block receives memory access requests from a plurality of memory clients, wherein the core logic block includes hierarchical validity database that stores indications as to data validity within the memory, wherein the core logic block updates the hierarchical validity database based on at least a portion of memory accesses that affect data coherency within the memory, wherein the core logic block consults the hierarchical validity database, and provides an indication as to data validity within the memory to ensure data coherency in response to memory access requests corresponding to memory read operations from at least one memory client.
A core logic block, comprising:
- a hierarchical validity database, wherein the hierarchical validity database includes:
- a first level, wherein the first level stores a plurality of lines, wherein each line of the plurality of lines in the first level corresponds to a division of a memory, wherein each line of the plurality of lines in the first level includes a plurality of bits and a division address, wherein the division address indicates to which division of the memory the line corresponds, wherein each bit included in each line within the first level indicates validity of a section of the division to which the line corresponds;
- and
- a second level, wherein the second level stores a plurality of lines, wherein each line of the plurality of lines in the second level corresponds to a section of the memory, wherein each line of the plurality of lines in the second level includes a plurality of bits and a section address, wherein the section address indicates to which section of the memory the line corresponds, wherein each bit included in each line within the second level indicates validity of a subsection of the section to which the line corresponds;
- and
- a memory access block operably coupled to the hierarchical validity database, wherein the memory access block receives memory access requests corresponding to the memory, wherein the memory access block verifies validity of data in the memory corresponding to memory access requests using the hierarchical validity database.
3 more elements
A method for data coherency maintenance, comprising:
- receiving a memory access request;
- determining validity of data in a memory corresponding to the memory access request using a hierarchical validity database, wherein the hierarchical validity database includes;
- a first level, wherein the first level stores a plurality of lines, wherein each line of the plurality of lines in the first level corresponds to a division of a memory, wherein each line of the plurality of lines in the first level includes a plurality of bits and a division address, wherein the division address indicates to which division of the memory the line corresponds, wherein each bit included in each line within the first level indicates validity of a section of the division to which the line corresponds;
- and
- a second level, wherein the second level stores a plurality of lines, wherein each line of the plurality of lines in the second level corresponds to a section of the memory, wherein each line of the plurality of lines in the second level includes a plurality of bits and a section address, wherein the section address indicates to which section of the memory the line corresponds, wherein each bit included in each line within the second level indicates validity of a subsection of the section to which the line corresponds;
- when validity of the data is confirmed, allowing the memory access request to proceed;
- and
- when validity of the data is not confirmed, issuing at least one cache coherency query to at least one client of a plurality of clients.
5 more elements
Dependencies are inferred from the claim text.