Multiple non-contiguous block erase in flash memory
AssigneeIntel Corporation
InventorRichard E. Fackenthal
Life of this patent
Estimating the term…
Abstract
A flash memory block erase operation permits multiple blocks to be erased simultaneously, even if the blocks are non-contiguous. A command sequence outputs multiple block addresses to the flash memory controller, which stores indicators of those addresses. When the command is completed, the flash memory initiates a block erase on all the specified blocks. The special command can be a multi-cycle bus command, made up of a sequence of single-cycle bus transfers using a standard format for the bus. The flash memory interface can contain the capability to interpret the command, retain the information transferred during the multiple bus cycles, and initiate the block erase operation after all the block addresses for that command have been received.
Claims28
A method, comprising:
- transmitting over a bus to a flash memory device an erase command that is a first command of a command sequence;
- transmitting over the bus to the flash memory device a plurality of addresses designating a plurality of memory blocks of the flash memory device, wherein the plurality of addresses are part of the command sequence;
- transmitting over the bus to the flash memory device a sequence termination command to initiate simultaneous erasure of the plurality of memory blocks of the flash memory device, wherein the sequence termination command is a last command of the command sequence, wherein the command sequence is discontinuous, wherein at least one bus cycle between the first command and the last command is available for other uses.
A machine-readable medium having stored thereon instructions which when executed by a processor cause the processor to perform operations comprising:
- transmitting over a bus to a flash memory device an erase command that is a first command of a command sequence;
- transmitting over the bus to the flash memory device a plurality of addresses designating a plurality of memory blocks of the flash memory device, wherein the plurality of addresses are part of the command sequence;
- transmitting over the bus to the flash memory device a sequence termination command to initiate simultaneous erasure of the plurality of memory blocks of the flash memory device, wherein the sequence termination command is a last command of the command sequence, wherein the command sequence is discontinuous, wherein at least one bus cycle between the first command and the last command is available for other uses.
A system, comprising:
- a bus;
- a processor coupled to the bus;
- a flash memory controller coupled to the bus, comprising:
- circuitry to receive a command sequence from the processor over a range of bus cycles that includes bus cycles not used by the command sequence, wherein an erase command is the first command of the command sequence and a sequence termination command is a last command of the command sequence;
- circuitry to receive a plurality of addresses from the processor that are part of the command sequence, wherein the plurality of addresses designate a plurality of memory blocks of a flash memory array coupled to the flash memory controller;
- circuitry to simultaneously erase the plurality of memory blocks in response to receipt of the sequence termination command;
- circuitry that permits the bus to be used by other devices during bus cycles not used by the command sequence.
Dependencies are inferred from the claim text.