Semiconductor device comprising CPU and peripheral circuit wherein control unit performs wait cycle control that makes peripheral circuit wait a predetermined time before responding to CPU
AssigneeMitsubishi Denki Kabushiki Kaisha
InventorsYasufumi Mori, Teruyuki Itou, Yukihiko Shimazu
Life of this patent
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Abstract
A semiconductor device includes a CPU and many peripheral circuits that are accessed by the CPU. Each peripheral circuit includes a wait control register which changeably holds wait cycle number information indicative of the number of wait cycles for an access by the CPU to that peripheral circuit, and a wait control circuit providing wait control for the access by the CPU to that peripheral circuit based on the number of wait cycles held by the wait control register.
Claims12
A semiconductor device having therein a CPU and at least one peripheral circuit accessed by said CPU, said semiconductor device comprising:
- a holding unit changeably holding information of number of wait cycles;
- and
- a control unit performing wait control for said at least one peripheral circuit so that said at least one peripheral circuit responds to said CPU based on the information of number of wait cycles.
A semiconductor device having therein a CPU and at least one peripheral circuit accessed by said CPU, said semiconductor device comprising:
- an input connection unit receiving, from outside of said semiconductor device, a designation signal designating number of wait cycles;
- and
- a control unit performing wait control for said at least one peripheral circuit so that said at least one peripheral circuit responds to said CPU based on the designation signal received via said input connection unit.
A semiconductor device having therein a CPU and at least one peripheral circuit accessed by said CPU, said semiconductor device comprising:
- a testing unit conducting a test for detecting data regarding number of wait cycles necessary for an access;
- and
- a control unit determining number of wait cycles based on the test by said testing unit and performing wait control for said at least one peripheral circuit so that said at least one peripheral circuit responds to said CPU based on the number of wait cycles determined.
A semiconductor device having therein a CPU and at least one peripheral circuit accessed by said CPU, said semiconductor device comprising:
- a power supply voltage detecting unit detecting a power supply voltage of said semiconductor device;
- and
- a control unit determining number of wait cycles based on the power supply voltage detected by said power supply voltage detecting unit, and performing wait control for said at least one peripheral circuit so that said at least one peripheral circuit responds to said CPU based on the number of wait cycles determined.
A semiconductor device having therein a CPU and at least one peripheral circuit accessed by said CPU, said semiconductor device comprising:
- an operation clock detecting unit detecting frequency of an operation clock signal for operating said semiconductor device;
- and
- a control unit determining number of wait cycles based on a detection result of said operation clock detecting unit, and performing wait control for said at least one peripheral circuit so that said at least one peripheral circuit responds to said CPU based on the number of wait cycles determined.
A semiconductor device having therein a CPU and at least one peripheral circuit accessed by said CPU, said semiconductor device comprising:
- an operation clock generation unit generating an operation clock for said at least one peripheral circuit, to operate said at least one peripheral circuit;
- and
- a control unit determining number of wait cycles based on frequency of the operation clock signal for the peripheral circuit generated by said operation clock generation unit and, wait control for said at least one peripheral circuit so that said at least one peripheral circuit responds to said CPU based on the number of wait cycles determined.
A computer readable medium for storing instructions, which, when executed by a computer, cause the computer to:
- change the number of wait cycles of an for response to said CPU from said at least one peripheral circuit based on
- a) frequency of an operation clock signal for operating a semiconductor device having therein said CPU and said at least one peripheral circuit accessed by said CPU, and
- b) any one of a power supply voltage of said semiconductor device and a frequency of an operation clock signal for said at least one peripheral circuit.
Dependencies are inferred from the claim text.