Information processor with snoop suppressing function, memory controller, and direct memory access processing method

An information processing apparatus comprising:

• a central processing unit,
• a cache memory,
• a main memory,
• a memory controller,
• a first bus connecting the cache memory and the memory controller
• an I/O device, and
• a second bus for interconnecting the memory controller and the I/O device;
• wherein the memory controller comprises a buffer memory for storing a plurality of addresses of past snoop accesses;
• and
• a direct memory access controller outputs a snoop access request to the first bus when a direct memory access requested by the I/O device is inconsistent with any one of the addresses stored in said buffer memory, and executes an access to the main memory corresponding to the direct memory access request by the I/O device.

A direct memory access processing method for an information processing apparatus having a first bus for interconnecting a central processing unit and a cache memory, a second bus for interconnecting an I/O device, a main memory, and a memory controller connected to the first and second buses and the main memory for controlling the main memory, the method comprising the steps of:

• making the memory controller store a plurality of predetermined ranges of addresses of direct past memory access requests received from the I/O device, in a buffer memory in the memory controller;
• upon reception of a direct memory access request from the I/O device, making the memory controller compares each of the addresses stored in the buffer memory with a predetermined range of an address used for the direct memory access;
• suppressing a snoop access process request from being sent to the cache memory if a comparison result indicates a coincidence;
• and
• accessing the main memory at an address requested by the direct memory access request and sending an access result to the I/O device.

A memory controller having first and second connection means for data transfer to an external and third connection means for connection to a storage unit, wherein a snoop process request signal is output to the first connection means when an access request to the storage unit is received from the second connection means, and after a response to the snoop process request signal is input to the first connection means, an access result to the storage unit corresponding to the access request is output to the second connection means, the memory controller comprising:

• a buffer memory for storing a plurality of predetermined ranges of addresses associated with past access requests input from the second connection means;
• means for judging whether the snoop process request signal is output or not, by comparing a predetermined range of an address associated with an access request input from the second connection means with the predetermined ranges of the addresses stored in said buffer memory;
• and
• means for suppressing the snoop process request signal from being output to the first connection means, in accordance with a judgment result by said judging means.