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US 6,748,456 B1Granted
PLD configuration port architecture and logic
AssigneeCypress Semiconductor Corporation
InventorsRichard L. Stanton, Anup Nayak, Navaz Lulla, Harish Dangat
Life of this patent
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Abstract
A programmable logic device (PLD) comprising a configuration controller. The configuration controller may be configured to (i) retrieve data and (ii) program a number of configuration bits of the PLD in response to the data.
Claims20
A programmable logic device comprising:
- a configuration controller configured to (i) retrieve data in response to one or more outputs of said programmable logic device and (ii) program a number of configuration bits of said programmable logic device in response to said data, wherein said data is retrieved (i) via a serial interface when said configuration controller is in a first mode, (ii) via a parallel interface when said configuration controller is in a second mode, and (iii) via a JTAG interface when said configuration controller is in a third mode.
A programmable logic device comprising:
- means for retrieving data in response to one or more outputs of said programmable logic device, wherein said data is retrieved (i) via a serial interface in a first mode, (ii) via a parallel interface in a second mode, and (iii) via a JTAG interface in a third mode;
- and
- means for programming a number of configuration bits of said programmable logic device in response to said data.
A method for configuring a programmable logic device comprising the steps of:
- (A) retrieving data in response to one or more outputs of said programmable logic device, wherein said data is retrieved (i) via a serial interface when in a first mode, (ii) via a parallel interface when in a second mode, and (iii) via a JTAG interface when in a third mode;
- (B) programming a number of configuration bits of said programmable logic device in response to said data.
Dependencies are inferred from the claim text.